David Harris
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7234abebef
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Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt
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2024-07-25 09:09:13 -07:00 |
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David Harris
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5bf7250687
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Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt
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2024-07-25 09:09:13 -07:00 |
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David Harris
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337e40ac1b
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Issue #894: trap on floating-point ops with reserved rounding modes
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2024-07-25 06:59:58 -07:00 |
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David Harris
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f7dd49cc6c
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Issue #894: trap on floating-point ops with reserved rounding modes
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2024-07-25 06:59:58 -07:00 |
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Jacob Pease
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02bb9b0b8b
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Fixed SDCCLK name discrepency.
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2024-07-24 22:48:31 -05:00 |
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Jacob Pease
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0dae881a0d
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Fixed SDCCLK name discrepency.
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2024-07-24 22:48:31 -05:00 |
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Jacob Pease
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a34836c08b
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Commented out references to old axi IP from wally.tcl.
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2024-07-24 22:47:15 -05:00 |
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Jacob Pease
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ebdf25a53b
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Commented out references to old axi IP from wally.tcl.
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2024-07-24 22:47:15 -05:00 |
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Jacob Pease
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ffec8cfb20
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Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram.
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2024-07-24 22:46:24 -05:00 |
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Jacob Pease
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2caf9e93be
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Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram.
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2024-07-24 22:46:24 -05:00 |
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Jacob Pease
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36d330a173
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Masked lower byte when writing to DLL.
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2024-07-24 22:44:27 -05:00 |
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Jacob Pease
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d15be492cb
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Masked lower byte when writing to DLL.
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2024-07-24 22:44:27 -05:00 |
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Jacob Pease
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a97c7f0b58
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Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future
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2024-07-24 22:43:47 -05:00 |
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Jacob Pease
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286d80de7e
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Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future
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2024-07-24 22:43:47 -05:00 |
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Jacob Pease
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e175a41863
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Added uart header to gpt.c.
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2024-07-24 22:43:16 -05:00 |
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Jacob Pease
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0107a400d1
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Added uart header to gpt.c.
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2024-07-24 22:43:16 -05:00 |
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Jordan Carlin
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308deba1fb
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Linux readme updates
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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4b86f85904
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Linux readme updates
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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204fd2e9ff
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Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed)
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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a9cd457536
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Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed)
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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6d77b22281
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Automatically determine number of threads to use in wally-tool-chain-install
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2024-07-24 20:19:30 -07:00 |
|
Jordan Carlin
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676c6b88a0
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Automatically determine number of threads to use in wally-tool-chain-install
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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602d126776
|
Build nproc linux
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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e6b3257862
|
Build nproc linux
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
|
c8519ce54f
|
Build testvectors with buildroot
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
|
85b98af958
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Build testvectors with buildroot
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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04b8739756
|
Add cpio to installation for buildroot
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2024-07-24 19:55:18 -07:00 |
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Jordan Carlin
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bbf90b1f4b
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Add cpio to installation for buildroot
|
2024-07-24 19:55:18 -07:00 |
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David Harris
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5ac02c79c6
|
Merge pull request #892 from ross144/main
Adds synthesizable RVVI FPGA hardware
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2024-07-24 12:21:36 -07:00 |
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David Harris
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2c7bc7038e
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Merge pull request #892 from ross144/main
Adds synthesizable RVVI FPGA hardware
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2024-07-24 12:21:36 -07:00 |
|
Rose Thompson
|
5a6e32576d
|
Fixed the reset bug in wallyTracer.
|
2024-07-24 13:32:46 -05:00 |
|
Rose Thompson
|
ce61429bdf
|
Fixed the reset bug in wallyTracer.
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2024-07-24 13:32:46 -05:00 |
|
Rose Thompson
|
994386f12c
|
Removed unused file.
|
2024-07-24 13:30:25 -05:00 |
|
Rose Thompson
|
5cae55561e
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Removed unused file.
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2024-07-24 13:30:25 -05:00 |
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Rose Thompson
|
9053923d92
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-07-24 13:14:25 -05:00 |
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Rose Thompson
|
df88939bcb
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-07-24 13:14:25 -05:00 |
|
Rose Thompson
|
13db14db6b
|
Factored out the rvvi testbench code into rvvitbwrapper.
|
2024-07-24 13:10:57 -05:00 |
|
Rose Thompson
|
d0a5b278b7
|
Factored out the rvvi testbench code into rvvitbwrapper.
|
2024-07-24 13:10:57 -05:00 |
|
Rose Thompson
|
c11036358a
|
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
|
2024-07-24 12:47:50 -05:00 |
|
Rose Thompson
|
b1a711ae0f
|
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
|
2024-07-24 12:47:50 -05:00 |
|
Rose Thompson
|
fb1869fcb9
|
Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
|
2024-07-24 10:13:03 -05:00 |
|
Rose Thompson
|
27f89fcdbd
|
Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
|
2024-07-24 10:13:03 -05:00 |
|
Jordan Carlin
|
07ac498623
|
Switch to logger function and fix exit codes
|
2024-07-23 23:42:03 -07:00 |
|
Jordan Carlin
|
bb5c9f9ead
|
Switch to logger function and fix exit codes
|
2024-07-23 23:42:03 -07:00 |
|
Jordan Carlin
|
4c0265f67d
|
Update logging grep
|
2024-07-23 23:40:42 -07:00 |
|
Jordan Carlin
|
d08deddcc4
|
Update logging grep
|
2024-07-23 23:40:42 -07:00 |
|
Jordan Carlin
|
76277d1e7d
|
Fix logging
|
2024-07-23 23:40:03 -07:00 |
|
Jordan Carlin
|
121ee51503
|
Fix logging
|
2024-07-23 23:40:03 -07:00 |
|
Jordan Carlin
|
790f566eaa
|
Remove hardcoded /opt/riscv
|
2024-07-23 23:29:45 -07:00 |
|
Jordan Carlin
|
47452ddaaa
|
Remove hardcoded /opt/riscv
|
2024-07-23 23:29:45 -07:00 |
|