Rose Thompson
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cde4598ed5
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Updated vcu108 and vcu118 scripts to corrects set the clock speed.
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2024-09-03 10:31:55 -07:00 |
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Rose Thompson
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702fa4e7bd
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Finally worked out that subtle bug in the tcl scripts clock setting.
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2024-09-03 10:30:34 -07:00 |
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David Harris
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ff9f0fa140
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Updated riscv-isac dependencies for security
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2024-09-03 03:46:44 -07:00 |
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David Harris
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b670f700ec
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Test push
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2024-09-03 03:37:33 -07:00 |
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Rose Thompson
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e29e1feed5
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Corrects merge error in Arty A7 clock speed.
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2024-09-02 15:01:41 -07:00 |
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Rose Thompson
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8375e168c0
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Removed file accidently readded.
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2024-09-02 14:48:36 -07:00 |
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Rose Thompson
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3a0e28fea0
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Added missing spi debugger.
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2024-09-02 14:47:31 -07:00 |
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Rose Thompson
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4afdb500d7
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Added missing files.
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2024-09-02 14:46:41 -07:00 |
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Rose Thompson
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d5e0382a81
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vcu108 build now starts with make vcu108 and selects the correct
memory size, starting address, device tree location, and clock speed
for the zsbl and synthesis scripts.
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2024-09-02 14:23:16 -07:00 |
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Rose Thompson
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869860bc55
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Merge branch 'main' of github.com:ross144/cvw
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2024-09-02 14:08:48 -07:00 |
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Rose Thompson
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9471ccd2fc
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Updated Makefiles and source files to build the zsbl according to the config.
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2024-09-02 14:03:47 -07:00 |
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Rose Thompson
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2e55f1cecc
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Well on the way to a fully automated FPGA build process which
correctly sets the clocks and memory locations.
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2024-09-02 11:19:02 -07:00 |
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David Harris
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5af07db76c
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-08-31 16:20:05 -07:00 |
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David Harris
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4f8fedad2e
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README update
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2024-08-30 13:37:18 -07:00 |
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Jordan Carlin
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0200b08418
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Merge pull request #940 from ross144/main
Merges Jordan's wally.do updates with the new fcov2 changes.
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2024-08-30 12:35:11 -07:00 |
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Jordan Carlin
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9e98c834f1
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Add lockstepverbose flag
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2024-08-30 12:32:41 -07:00 |
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Rose Thompson
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65e338e762
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Merges Jordan's wally.do updates with the new fcov2 changes. Updates
cvw-arch-verif commit.
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2024-08-30 12:31:26 -07:00 |
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Rose Thompson
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6f7d4cde21
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Merge pull request #908 from jordancarlin/script_updates
Sim updates + rv64gcCacheSim.py fixed
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2024-08-30 12:25:44 -07:00 |
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Rose Thompson
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5fb3b386f5
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Merge pull request #939 from JacobPease/main
Fixed Arty constraints and corrected typos.
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2024-08-30 12:23:53 -07:00 |
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Jacob Pease
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4b8d35bd8a
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-30 14:18:54 -05:00 |
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Jacob Pease
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4acac08320
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Fixed Arty constraints and corrected typos.
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2024-08-30 14:17:37 -05:00 |
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Jordan Carlin
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4929581576
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Cleanup
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2024-08-30 11:57:31 -07:00 |
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Rose Thompson
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f1d9e18dee
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Modified fpga config to support two fpga boards with different amount of memory.
Modified vcu108 constraints to better constrain the spi clock and in/out.
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2024-08-29 16:12:58 -07:00 |
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Jordan Carlin
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80750f2308
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Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates
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2024-08-29 15:55:54 -07:00 |
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David Harris
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a9d904caf1
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-08-29 15:43:04 -07:00 |
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David Harris
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ffd4d71fe5
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Merge pull request #938 from ross144/main
Fixed basic support for open source riscvISACOV
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2024-08-29 15:42:40 -07:00 |
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Rose Thompson
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587a65aa75
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-29 15:30:45 -07:00 |
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Rose Thompson
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e07f303353
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Have basic rv32gc functional coverage running with open source riscvISACOV.
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2024-08-29 15:29:04 -07:00 |
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David Harris
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6157023d16
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-08-29 15:07:18 -07:00 |
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David Harris
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636a8cbbd6
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Merge pull request #937 from ross144/main
Fixed questa and ImperasDV library issue
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2024-08-29 15:00:18 -07:00 |
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Rose Thompson
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dc9a77e45a
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Updated riscvISACOV submodule to https instead of ssh.
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2024-08-29 14:54:47 -07:00 |
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Rose Thompson
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a1c6bc854e
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Fixed a subtle questa sim bug with imperasDV. On some linux systems
vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV
libraries are 64-bit. vsim must run in 64-bit mode.
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2024-08-29 14:00:52 -07:00 |
|
David Harris
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0e9e7d0a49
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Fixed wallyTracer floating-point register FLEN
|
2024-08-29 11:11:19 -07:00 |
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Rose Thompson
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0ce4d1b452
|
Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-29 10:50:27 -07:00 |
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Rose Thompson
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6ad2c2e7a6
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Merge pull request #935 from davidharrishmc/dev
Added lockstep support for RV32. Not all wally privileged tests pass…
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2024-08-29 10:45:17 -07:00 |
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David Harris
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26f3c2a607
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Added lockstep support for RV32. Not all wally privileged tests pass yet
|
2024-08-29 10:44:37 -07:00 |
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David Harris
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ca4dcfdaa9
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Merge pull request #934 from JacobPease/main
Custom test spitest fix
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2024-08-28 02:13:06 -07:00 |
|
Jacob Pease
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c4d909c412
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-28 04:10:38 -05:00 |
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Jacob Pease
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3b91977227
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Added start.s to spitest directory.
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2024-08-28 04:10:24 -05:00 |
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Rose Thompson
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cb05697698
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Added basic SPI signals to waveform.
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2024-08-27 15:51:19 -07:00 |
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Rose Thompson
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7e16ddd859
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Improved fpga synth script.
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2024-08-27 15:50:05 -07:00 |
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Rose Thompson
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e5d3462a90
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Converted wall.tcl to entirely project mode.
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2024-08-27 14:15:58 -07:00 |
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Rose Thompson
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0ce289c937
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Merge pull request #933 from JacobPease/main
Committing the custom test spitest.
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2024-08-27 12:43:19 -07:00 |
|
Jacob Pease
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44ece7cb96
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Added CVW header to spitest files.
|
2024-08-27 14:28:49 -05:00 |
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Jacob Pease
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b7a74307c5
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Committing the custom test spitest.
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2024-08-27 14:19:56 -05:00 |
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Rose Thompson
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2dd897e7e1
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Merge pull request #932 from davidharrishmc/dev
Added temporary --fcov2 option to start adopting open-source riscvISACOV
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2024-08-27 08:47:59 -07:00 |
|
David Harris
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9df38e14b2
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Added temporary --fcov2 option to start adopting open-source riscvISACOV
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2024-08-27 08:40:44 -07:00 |
|
Rose Thompson
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f20a1564fa
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Added SPI debugger.
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2024-08-26 17:22:13 -07:00 |
|
Rose Thompson
|
f31eb62c1b
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Merge pull request #929 from JacobPease/main
Bootloader Speed Improvements
|
2024-08-26 09:10:42 -07:00 |
|
Jordan Carlin
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0c4993e1db
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Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates
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2024-08-25 14:57:22 -07:00 |
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