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Author SHA1 Message Date
Jacob Pease
36d330a173 Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
d15be492cb Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
a97c7f0b58 Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
286d80de7e Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
e175a41863 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Jacob Pease
0107a400d1 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Jordan Carlin
308deba1fb Linux readme updates 2024-07-24 20:19:30 -07:00
Jordan Carlin
4b86f85904
Linux readme updates 2024-07-24 20:19:30 -07:00
Jordan Carlin
204fd2e9ff Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed) 2024-07-24 20:19:30 -07:00
Jordan Carlin
a9cd457536
Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed) 2024-07-24 20:19:30 -07:00
Jordan Carlin
6d77b22281 Automatically determine number of threads to use in wally-tool-chain-install 2024-07-24 20:19:30 -07:00
Jordan Carlin
676c6b88a0
Automatically determine number of threads to use in wally-tool-chain-install 2024-07-24 20:19:30 -07:00
Jordan Carlin
602d126776 Build nproc linux 2024-07-24 20:19:30 -07:00
Jordan Carlin
e6b3257862
Build nproc linux 2024-07-24 20:19:30 -07:00
Jordan Carlin
c8519ce54f Build testvectors with buildroot 2024-07-24 20:19:30 -07:00
Jordan Carlin
85b98af958
Build testvectors with buildroot 2024-07-24 20:19:30 -07:00
Jordan Carlin
04b8739756 Add cpio to installation for buildroot 2024-07-24 19:55:18 -07:00
Jordan Carlin
bbf90b1f4b
Add cpio to installation for buildroot 2024-07-24 19:55:18 -07:00
David Harris
5ac02c79c6 Merge pull request #892 from ross144/main 
Adds synthesizable RVVI FPGA hardware
 2024-07-24 12:21:36 -07:00
David Harris
2c7bc7038e
Merge pull request #892 from ross144/main 
Adds synthesizable RVVI FPGA hardware
 2024-07-24 12:21:36 -07:00
Rose Thompson
5a6e32576d Fixed the reset bug in wallyTracer. 2024-07-24 13:32:46 -05:00
Rose Thompson
ce61429bdf Fixed the reset bug in wallyTracer. 2024-07-24 13:32:46 -05:00
Rose Thompson
994386f12c Removed unused file. 2024-07-24 13:30:25 -05:00
Rose Thompson
5cae55561e Removed unused file. 2024-07-24 13:30:25 -05:00
Rose Thompson
9053923d92 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-24 13:14:25 -05:00
Rose Thompson
df88939bcb Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-24 13:14:25 -05:00
Rose Thompson
13db14db6b Factored out the rvvi testbench code into rvvitbwrapper. 2024-07-24 13:10:57 -05:00
Rose Thompson
d0a5b278b7 Factored out the rvvi testbench code into rvvitbwrapper. 2024-07-24 13:10:57 -05:00
Rose Thompson
c11036358a Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Rose Thompson
b1a711ae0f Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Rose Thompson
fb1869fcb9 Updated verilog-ethernet to remove all verilator warnings or at least suppress them. 2024-07-24 10:13:03 -05:00
Rose Thompson
27f89fcdbd Updated verilog-ethernet to remove all verilator warnings or at least suppress them. 2024-07-24 10:13:03 -05:00
Jordan Carlin
07ac498623 Switch to logger function and fix exit codes 2024-07-23 23:42:03 -07:00
Jordan Carlin
bb5c9f9ead
Switch to logger function and fix exit codes 2024-07-23 23:42:03 -07:00
Jordan Carlin
4c0265f67d Update logging grep 2024-07-23 23:40:42 -07:00
Jordan Carlin
d08deddcc4
Update logging grep 2024-07-23 23:40:42 -07:00
Jordan Carlin
76277d1e7d Fix logging 2024-07-23 23:40:03 -07:00
Jordan Carlin
121ee51503
Fix logging 2024-07-23 23:40:03 -07:00
Jordan Carlin
790f566eaa Remove hardcoded /opt/riscv 2024-07-23 23:29:45 -07:00
Jordan Carlin
47452ddaaa
Remove hardcoded /opt/riscv 2024-07-23 23:29:45 -07:00
Rose Thompson
7960f26e84 Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings. 2024-07-23 17:44:37 -05:00
Rose Thompson
9404a339ee Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings. 2024-07-23 17:44:37 -05:00
Rose Thompson
35efbd6a54 Changes are confirmed to work on the FPGA. 2024-07-23 17:39:38 -05:00
Rose Thompson
6c212ebf0e Changes are confirmed to work on the FPGA. 2024-07-23 17:39:38 -05:00
Jacob Pease
c18b3d814d Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Jacob Pease
f1cc7dd5a3 Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Jacob Pease
23d9c7a486 Fixed syntax bugs. inline functions are now static and in the spi.h header. 2024-07-23 17:00:32 -05:00
Jacob Pease
dcb2edf888 Fixed syntax bugs. inline functions are now static and in the spi.h header. 2024-07-23 17:00:32 -05:00
Rose Thompson
bfb3b63a24 Code cleanup. 2024-07-23 16:35:05 -05:00
Rose Thompson
e8e71ad643 Code cleanup. 2024-07-23 16:35:05 -05:00