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Author	SHA1	Message	Date
Ross Thompson	c8a5d61cbb	new cache bus fsm not working but lints. ... Forgot a few files in the last commit.	2022-08-30 10:58:07 -05:00
Ross Thompson	5eb1fff27d	Have a rough working multi manager!	2022-08-29 17:11:27 -05:00
Ross Thompson	4f40bd07c3	Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu.	2022-08-29 17:04:53 -05:00
Ross Thompson	4d7b905806	Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.	2022-08-29 13:01:24 -05:00
Ross Thompson	40cf4a9ea9	Typo.	2022-08-29 11:40:35 -05:00
Ross Thompson	1c9aed2e7e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-29 11:38:37 -05:00
Ross Thompson	9a7c7e8398	Added comments about planned changes.	2022-08-29 09:48:00 -05:00
David Harris	6961e499dc	Renamed special case	2022-08-29 04:29:58 -07:00
David Harris	81ec1ac858	Separated out radix 2 and radix 4 stages into different modules	2022-08-29 04:26:14 -07:00
David Harris	b4cb9a678a	renamed srt to fdivsqrt	2022-08-29 04:04:05 -07:00
Ross Thompson	35d0b759d1	Removed ignore request from busfsm.	2022-08-28 21:12:27 -05:00
Ross Thompson	dd00474956	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
Ross Thompson	e3e1f29428	Reordered the adrdecs.	2022-08-28 13:38:57 -05:00
Ross Thompson	99e0e5c817	Possible fix.	2022-08-28 13:10:47 -05:00
Ross Thompson	5e77b1bd2b	Partial fix to bus + dtim.	2022-08-27 23:44:17 -05:00
David Harris	35d0a951d2	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
David Harris	3959902c5b	Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus	2022-08-27 05:31:56 -07:00
David Harris	e526fea68a	fixed wally-config	2022-08-26 22:13:10 -07:00
David Harris	bd6f2444cd	Fixed address decoder hanging buildroot	2022-08-26 22:01:25 -07:00
David Harris	bf2c20cd17	Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs	2022-08-26 21:29:26 -07:00
David Harris	76006825b3	Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding	2022-08-26 21:18:18 -07:00
David Harris	921a49921b	Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM	2022-08-26 21:05:20 -07:00
David Harris	460a95f99b	Added IROM and DTIM decoding to adrdecs	2022-08-26 20:45:43 -07:00
David Harris	6409548c8b	Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each	2022-08-26 20:26:12 -07:00
David Harris	906f6f2990	Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem	2022-08-26 20:12:03 -07:00
David Harris	841eae58ca	Fixed endian swapping on bus only	2022-08-26 19:58:04 -07:00
David Harris	af2e71046e	Fixed rv32e LSU and IFU issues	2022-08-25 20:02:38 -07:00
David Harris	8cbdbb1c38	lsu simplification	2022-08-25 18:52:42 -07:00
David Harris	d507bb3d70	busfsm simplified	2022-08-25 18:36:53 -07:00
David Harris	dc52f55aa6	Removed unused signals	2022-08-25 18:34:39 -07:00
David Harris	50826c0b61	Removed unused signals	2022-08-25 18:30:46 -07:00
David Harris	7cbca2dd22	Removed UncachedBusRead and UncachedBusWrite	2022-08-25 18:24:39 -07:00
David Harris	845807a329	Restored ahbtranstype	2022-08-25 18:22:26 -07:00
David Harris	4ab678ed48	Removed ahbtranstype	2022-08-25 18:21:45 -07:00
David Harris	f405a191af	Removed WordCountFlag	2022-08-25 18:21:18 -07:00
David Harris	db7698202d	Removed UncachedAccess	2022-08-25 18:20:52 -07:00
David Harris	7801ed48b3	Removed UncachedRW	2022-08-25 18:19:41 -07:00
David Harris	bb4ae908db	Removed CacheBusAck	2022-08-25 18:17:34 -07:00
David Harris	85b5587678	Removed SelUncachedAdr	2022-08-25 18:15:59 -07:00
David Harris	555083b0c3	Removed Cache_Enabled	2022-08-25 18:13:34 -07:00
David Harris	b982db5bd5	Removed STATE_BUS_FETCH and STATE_BUS_WRITE	2022-08-25 18:12:09 -07:00
David Harris	de9ec7cc2e	Removed CacheFetchLine and CacheWriteLine	2022-08-25 18:10:15 -07:00
David Harris	fb5ddc476c	Removed CountEn	2022-08-25 18:05:44 -07:00
David Harris	7eae6765df	Removed wordcount	2022-08-25 18:04:49 -07:00
David Harris	73419f0d41	Added buscachefsm for system with bus and cache	2022-08-25 18:01:01 -07:00
David Harris	0b918d6916	Separated busdp for cache from simpler logic for no cache	2022-08-25 17:54:04 -07:00
David Harris	5c1934208a	Simplified swbytemask	2022-08-25 17:32:16 -07:00
David Harris	352bf88ac0	FIxed wallypipelinedsoc merge conflict	2022-08-25 15:36:47 -07:00
David Harris	b96942e84c	Removed delayed AHB signals from top level	2022-08-25 15:34:14 -07:00
Ross Thompson	109bcd470e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 16:01:02 -05:00