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Simplified swbytemask

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This commit is contained in:
David Harris 2022-08-25 17:32:16 -07:00
parent 352bf88ac0
commit 5c1934208a
4 changed files with 16 additions and 70 deletions
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12
pipelined/src/ebu/ahblite.sv
View File

@ -75,11 +75,13 @@ module ahblite (
(* mark_debug = "true" *) output logic HMASTLOCK
);
localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator
typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
statetype BusState, NextBusState;
logic LSUGrant;
logic [2:0] HADDRD;
logic [3:0] HSIZED;
logic [ADRBITS-1:0] HADDRD;
logic [1:0] HSIZED;
assign HCLK = clk;
assign HRESETn = ~reset;
@ -123,9 +125,9 @@ module ahblite (
flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
// Byte mask for HWSTRB based on delayed signals
flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD), .ByteMask(HWSTRB));
flop #(ADRBITS) adrreg(HCLK, HADDR[ADRBITS-1:0], HADDRD);
flop #(2) sizereg(HCLK, HSIZE[1:0], HSIZED);
swbytemask swbytemask(.Size({1'b0, HSIZED}), .Adr(HADDRD), .ByteMask(HWSTRB));
// Send control back to IFU and LSU
assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD);

2
pipelined/src/lsu/lsu.sv
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@ -284,7 +284,7 @@ module lsu (
.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
// Compute byte masks
swbytemaskword #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
swbytemask #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
/////////////////////////////////////////////////////////////////////////////////////////////
// MW Pipeline Register

13
pipelined/src/lsu/swbytemask.sv
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@ -30,11 +30,14 @@
`include "wally-config.vh"
module swbytemask (
input logic [1:0] Size,
input logic [2:0] Adr,
output logic [`XLEN/8-1:0] ByteMask);
module swbytemask #(parameter WORDLEN = `XLEN)(
input logic [2:0] Size,
input logic [$clog2(WORDLEN/8)-1:0] Adr,
output logic [WORDLEN/8-1:0] ByteMask);
assign ByteMask = ((2**(2**Size))-1) << Adr;
/* Equivalent to the following
if(`XLEN == 64) begin
always_comb begin
@ -62,5 +65,5 @@ module swbytemask (
endcase
end
end
*/
endmodule

59
pipelined/src/lsu/swbytemaskword.sv
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@ -1,59 +0,0 @@
///////////////////////////////////////////
// swbytemask.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: On-chip RAM, external to core
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// MIT LICENSE
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
// to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR CO///////////////////////////////////////////
// swbytemask.sv
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module swbytemaskword #(parameter WORDLEN = 64)(
input logic [2:0] Size,
input logic [$clog2(WORDLEN/8)-1:0] Adr,
output logic [WORDLEN/8-1:0] ByteMask);
assign ByteMask = ((2**(2**Size))-1) << Adr;
/* Equivalent to the following for WORDLEN = 64
if(WORDLEN == 64) begin
always_comb begin
case(Size[1:0])
2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
2'b01: case (Adr[2:1])
2'b00: ByteMask = 8'b0000_0011;
2'b01: ByteMask = 8'b0000_1100;
2'b10: ByteMask = 8'b0011_0000;
2'b11: ByteMask = 8'b1100_0000;
endcase
2'b10: if (Adr[2]) ByteMask = 8'b11110000;
else ByteMask = 8'b00001111;
2'b11: ByteMask = 8'b1111_1111;
default ByteMask = 8'b0000_0000;
endcase
end
end
*/
endmodule