David Harris
283c2cda0e
added or.sv
2021-07-13 13:26:40 -04:00
Katherine Parry
b9edbb15eb
Fixed writting MStatus FS bits
2021-07-13 13:22:04 -04:00
Katherine Parry
acdd2e4504
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
David Harris
3427d2b7d6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 13:19:24 -04:00
David Harris
68d1f87101
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
bbracker
90eb84cc61
updated buildroot make procedure to incorporate configs more robustly
2021-07-13 12:40:14 -04:00
Ross Thompson
40922cf064
Fixed subword write. subword read should not feed into subword write.
2021-07-13 11:21:44 -05:00
Ross Thompson
a314b3cf68
restored rv64ic config back to full sized dtim.
2021-07-13 11:18:54 -05:00
Ross Thompson
d3ffbe0e5d
Modularized the shadow memory to reduce performance hit.
2021-07-13 10:55:57 -05:00
Ross Thompson
17dc488010
Got the shadow ram cache flush working.
2021-07-13 10:03:47 -05:00
bbracker
471fe8ab31
whoops I accidentally made main.config into a symbolic link; now it is a source file
2021-07-13 11:00:01 -04:00
bbracker
be81912c52
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 10:04:13 -04:00
bbracker
497d8e3f16
working config for a buildroot that boots
2021-07-13 10:04:09 -04:00
David Harris
4be1e8617f
Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
2021-07-13 09:32:02 -04:00
Ross Thompson
9fe6190763
Team work on solving the dcache data inconsistency problem.
2021-07-12 23:46:32 -05:00
Ross Thompson
6b42b93886
Now updates the dtim with the dirty data in the dcache.
...
Simulation is showing issues. It lookslike the cache is not
evicting the correct data.
2021-07-12 15:13:27 -05:00
Ross Thompson
8ca8b9075d
Progress towards the test bench flush.
2021-07-12 14:22:13 -05:00
Katherine Parry
a4bd128978
fcvt.sv cleanup
2021-07-11 21:30:01 -04:00
Katherine Parry
0cc07fda1b
Almost all convert instructions pass Imperas tests
2021-07-11 18:06:33 -04:00
bbracker
05f9fa65bf
rootfs.cpio no longer overlaps
2021-07-11 05:11:12 -04:00
Ross Thompson
282bde7205
Fixed the spurious AHB requests to address 0. Somehow by not having a default
...
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
2021-07-10 22:34:47 -05:00
Ross Thompson
d9fa3af94d
Loads are working.
...
There is a bug when the icache stalls 1 cycle before the d cache.
2021-07-10 22:15:44 -05:00
Ross Thompson
a82c4c99c2
Actually writes the correct data now on stores.
2021-07-10 17:48:47 -05:00
Ross Thompson
ee72178eec
Write miss with eviction works.
2021-07-10 15:17:40 -05:00
Ross Thompson
0a6c86af94
Write Hits and Write Misses without eviction are working correctly! The next
...
step is to add eviction of dirty lines.
2021-07-10 10:56:25 -05:00
bbracker
e77a9169b6
greatly stripped down unused stuff in linux config
2021-07-10 11:53:35 -04:00
David Harris
488cfa16ff
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 19:18:35 -04:00
David Harris
e6fb590187
added missing tlbmixer.sv
2021-07-09 19:18:23 -04:00
bbracker
4556098f0a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 18:56:28 -04:00
bbracker
e4f62e32ba
fix_mem.py bugfix
2021-07-09 18:56:17 -04:00
Ross Thompson
94b29ec418
Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.
...
I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
2021-07-09 17:14:54 -05:00
bbracker
b2cb86d55c
organize/update buildroot scripts for new image
2021-07-09 17:03:47 -04:00
Ross Thompson
7e98610651
Design loads in modelsim, but trap is an X.
2021-07-09 15:37:16 -05:00
Ross Thompson
6abd23a61d
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
Kip Macsai-Goren
7e5a9f141a
comment clean up to match textbook chapter
2021-07-09 12:54:09 -04:00
David Harris
ef2bcf6ea7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 07:53:30 -04:00
David Harris
b09fd0d0a8
Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
David Harris
4d53a935b3
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
bbracker
5736fdecbb
organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
2021-07-08 19:18:11 -04:00
Ross Thompson
2efb7a4f81
Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.
2021-07-08 18:03:52 -05:00
Ross Thompson
6041aef263
completed read miss branch through dcache fsm.
...
The challenge now is to connect to ahb and lsu.
2021-07-08 17:53:08 -05:00
David Harris
230654ea76
Eliminate reserved bits from TLB RAM
2021-07-08 17:35:00 -04:00
David Harris
f806707cb0
Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
2021-07-08 16:58:11 -04:00
David Harris
b1592a0542
TLB cleanup to match diagrams
2021-07-08 16:52:06 -04:00
Ross Thompson
4c5aee3042
This d cache fsm is getting complex.
2021-07-08 15:26:16 -05:00
Ross Thompson
adcc7afffa
Partial implementation of the data cache. Missing the fsm.
2021-07-07 17:52:16 -05:00
David Harris
dc44ca4b0b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-07 06:32:29 -04:00
David Harris
6dc49dd073
Renamed tlb ReadLines to Matches
2021-07-07 06:32:26 -04:00
Abe
09a092abd5
Updated MISA defining as well as porting sizes for peripherals (34 to 56)
2021-07-07 02:37:09 -04:00
Abe
ed3c06b851
Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time.
2021-07-07 02:28:11 -04:00
