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Configurable RISC-V Processor
1,228 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.3%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
6b42b93886
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Ross Thompson 6b42b93886 Now updates the dtim with the dirty data in the dcache. 
Simulation is showing issues.  It lookslike the cache is not
evicting the correct data.
2021-07-12 15:13:27 -05:00
riscv-coremark Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs 2021-06-25 16:42:03 -04:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined Now updates the dtim with the dirty data in the dcache. 2021-07-12 15:13:27 -05:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore split intermediate GDB output file into smaller files for better debug experience 2021-06-26 07:18:26 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor