Ross Thompson
4b4cee3ddd
Added correct stop condition for coremark.
2022-02-02 09:53:51 -06:00
Ross Thompson
143bdaa288
Modified makefiles to generate function address to name mappings for modelsim.
2022-02-01 18:25:03 -06:00
Ross Thompson
f055441ecf
Improved function_radix to not printout warnings when no valid function is found.
2022-02-01 18:03:09 -06:00
Ross Thompson
5407b72af9
Setup the main regression test to be able to handle coremark.
2022-02-01 17:00:11 -06:00
Ross Thompson
6c5b0bec40
More cleanup of IFU.
2022-02-01 14:32:27 -06:00
Ross Thompson
85d510e315
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-01 10:50:38 -06:00
Ross Thompson
73edd50120
Updated fpga's bootloader to reflect the changes to the gpio address change.
2022-02-01 10:43:24 -06:00
Ross Thompson
1f0821da0d
IFU and LSU now share the same busdp module.
2022-01-31 16:25:41 -06:00
Ross Thompson
86bac2a083
partial ifu cleanup.
2022-01-31 16:08:53 -06:00
Ross Thompson
e4ee630a3e
cleanup.
2022-01-31 13:29:04 -06:00
Ross Thompson
5ce8dd60c5
Fixed modelsim warning with linux simulation.
2022-01-31 12:57:02 -06:00
Ross Thompson
c9a163b8fd
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
4422e2f91c
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
c2b2fae98d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-31 12:17:37 -06:00
Ross Thompson
f4e62bcb54
Cleanup busdp.
2022-01-31 12:17:07 -06:00
Ross Thompson
31da37dd0f
Moved lsu virtual memory logic into separate module.
2022-01-31 11:56:03 -06:00
Ross Thompson
9cd502d0af
Encapsulated dtim.
2022-01-31 11:23:55 -06:00
Ross Thompson
c939eb20eb
Removed unused signals in the LSU.
2022-01-31 10:35:35 -06:00
Ross Thompson
5fe30ff8a9
Moved atomic logic to own module.
2022-01-31 10:28:12 -06:00
Ross Thompson
a4f6653cd8
Encapsulated the bus data path into a separate module.
2022-01-31 10:15:48 -06:00
Kip Macsai-Goren
242b27705d
added machine info test that uses new test library
2022-01-31 05:54:43 +00:00
David Harris
090533cfe9
Replaced || and && with | and &
2022-01-31 01:07:35 +00:00
Ross Thompson
ac50a36aac
LSU and IFU cleanup.
2022-01-28 15:26:06 -06:00
Ross Thompson
2e00186eea
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
42d60235f0
Clean up of mmu instances in IFU and LSU.
2022-01-28 14:02:05 -06:00
Ross Thompson
c5e0024e9f
Moved spills to own module.
2022-01-28 13:40:35 -06:00
Ross Thompson
06209c417f
Cleaned up the InstrMisalignedFault.
2022-01-28 13:19:24 -06:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
d15cb64bdf
Relocated the misalignment faults.
2022-01-27 16:03:00 -06:00
David Harris
30cc27e719
IFU cleanup
2022-01-27 17:18:55 +00:00
David Harris
5ab06fef20
IFU cleanup
2022-01-27 16:41:57 +00:00
David Harris
bdd5796f3a
Optimized out second adder from IFU for PC+2
2022-01-27 16:06:24 +00:00
David Harris
7f91170bab
Comments in LSU code about restructuring
2022-01-27 15:53:59 +00:00
Ross Thompson
b44f57b6b5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-27 08:45:33 -06:00
Ross Thompson
284d671da3
Increased number of concurrent tests.
2022-01-27 08:45:25 -06:00
David Harris
448acedd8b
Set up rv32emc config
2022-01-27 14:37:58 +00:00
Ross Thompson
db0a0bd29e
BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush.
2022-01-27 07:59:59 -06:00
Ross Thompson
3ebcd35a8c
Added colors to regression script to make it easy to pick out success from fail.
2022-01-26 22:40:32 -06:00
Ross Thompson
cc5a9a015b
Removed mux in PCNextF logic. Minor IFU improvements.
2022-01-26 22:33:26 -06:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
Ross Thompson
fc86651937
IFU simplifications.
2022-01-26 13:54:59 -06:00
David Harris
748375c82f
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
David Harris
21bdce63ff
Testgen working for Lab 2
2022-01-26 18:01:51 +00:00
Ross Thompson
840e814e95
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
David Harris
8d04e83c9f
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
9da1ed4ed9
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
a86a9f5c2a
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
e3136c9a1e
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
7ad2eb009a
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
6a555032eb
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
David Harris
cf50beb958
Start of IFU cleanup
2022-01-25 17:31:53 +00:00
Ross Thompson
8ef70389d3
Added spill support back into the IROM IFU.
2022-01-21 15:50:54 -06:00
Ross Thompson
9982549057
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
0ceaf792ed
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-21 00:12:18 +00:00
David Harris
39d318fb2a
Fixed path to riscvOVPsimPlus
2022-01-21 00:12:14 +00:00
Ross Thompson
e2343699d1
Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
2022-01-20 16:39:54 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
cea09aab98
Removed imperas tests from makefile for now
2022-01-20 14:51:56 +00:00
David Harris
fc932ef0ff
Added top-level make clean
2022-01-20 14:17:26 +00:00
David Harris
d5f12195c8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-20 00:04:27 +00:00
Ross Thompson
acec56c27e
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
David Harris
9b29710990
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-19 00:26:34 +00:00
Ross Thompson
4a75e69457
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
Ross Thompson
28859f959b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-18 17:19:59 -06:00
Ross Thompson
a5f773220e
Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
2022-01-18 17:19:33 -06:00
David Harris
ebf9f5d526
riscvsingle reparittioned to match Ch4
2022-01-17 16:57:32 +00:00
David Harris
55b4423329
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
b63e53bbdb
Defined rv32e and rv32emc configs
2022-01-17 14:01:01 +00:00
David Harris
bd320c2f76
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
325724f556
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
6febce0001
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
fd13272d4c
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
David Harris
db2271b7e0
LSU cleanup
2022-01-15 00:11:30 +00:00
David Harris
dab3c754d7
LSU cleanup
2022-01-15 00:03:03 +00:00
David Harris
2bf4676ff8
LSU cleanup
2022-01-14 23:55:27 +00:00
Ross Thompson
03010845f5
Fixed spillthreshold warning.
2022-01-14 17:23:39 -06:00
Ross Thompson
ba10e9dfe8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-14 17:16:53 -06:00
David Harris
43abf25417
moved fp to tests
2022-01-14 23:05:59 +00:00
David Harris
218a8e6eaa
LSU partitioning
2022-01-14 23:02:28 +00:00
David Harris
ae6792e354
Moved fp tests from testbench to tests/fp
2022-01-14 23:00:46 +00:00
Ross Thompson
73ad5715f4
Cleanup IFU comments.
2022-01-14 15:06:30 -06:00
Ross Thompson
b8f4eb2997
Optimization in the ifu. Please note this optimization is not strictly correct,
...
but is possible. See comments in the ifu source code for details.
2022-01-14 12:16:48 -06:00
Ross Thompson
2e8f5e06bd
More ifu cleanup.
2022-01-14 11:19:12 -06:00
Ross Thompson
3bec276862
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
James E. Stine
e0e30c1e9e
Update to TestFloat for scripts so can run automatically once
...
TestFloat/Softfloat is compiled. Slight change to the README as well.
2022-01-14 09:25:37 -06:00
Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
David Harris
602867f54e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-13 21:46:00 +00:00
David Harris
7d13740a11
Mixed C and assembly language test cases; SRT initial version passing tests
2022-01-13 21:45:54 +00:00
Ross Thompson
e6e3b0607a
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
f870b8b3d3
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
Ross Thompson
66f3259984
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
a23e6efd5c
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
85b5dc08a8
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
e06fb923a1
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
11f1613d59
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
d8173745bb
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
cd75bf98e1
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
b294f1fbb0
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-12 14:17:16 -06:00
Ross Thompson
459f4bd3b4
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
960af4b70f
Set rv32ic to not use icache.
2022-01-12 14:10:09 -06:00
Ross Thompson
f18684efbf
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-12 13:29:19 -06:00
Ross Thompson
786a772444
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
Kip Macsai-Goren
c251144460
Fixed PMA regions, Added passing PMA tests to regression
2022-01-10 22:08:26 +00:00
David Harris
3a2b459439
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
401a5b1779
Removed unused coremark_bare
2022-01-10 05:05:55 +00:00
David Harris
39d5570d2c
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
04ea93aa27
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
ae927e2bc6
Fixed wavefile.
...
Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
David Harris
0212260eef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
54d852f6ae
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
bea6d0856d
Testbench directory cleanup
2022-01-07 17:02:16 +00:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
fedb9d3287
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
40af3abef9
piplined directory cleanup
2022-01-07 12:43:50 +00:00
David Harris
c97572d209
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
Ross Thompson
c8d47fc7c3
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
David Harris
2a64b1bc95
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
0fddceffa6
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
0e023e29d8
Code cleanup
2022-01-07 04:07:04 +00:00
Ross Thompson
c9c3bddc6d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 17:19:20 -06:00
Ross Thompson
008ac20a43
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
David Harris
08231d4e66
Tests cleanup:
2022-01-06 23:07:22 +00:00
David Harris
cb68548b88
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
fc4db84bbc
Makefile make allclean
2022-01-06 23:04:30 +00:00
David Harris
e5f9fbb238
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
Katherine Parry
b3ebce0365
some FPU test fixes
2022-01-06 23:03:20 +00:00
Ross Thompson
e1db967417
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
David Harris
1c96b22b8f
More FP unpacking fix
2022-01-06 22:22:22 +00:00
David Harris
2b8e8707a7
Floating point test cleanup
2022-01-06 21:45:16 +00:00
David Harris
2b4c81fe98
Fixed unpacking bug; regression runs again
2022-01-06 18:22:30 +00:00
David Harris
55e757db03
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 18:10:32 +00:00
David Harris
c9aa21d5a3
FPU debug and configurable logic cleanup
2022-01-06 18:10:25 +00:00
Ross Thompson
d30ad136f3
cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
2022-01-05 22:56:18 -06:00
Ross Thompson
365b2715ed
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
77efcad15b
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
5a2ae561a7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
Ross Thompson
3517db6b64
Fixed xilinx synth error with $error in extend.sv
2022-01-05 17:48:08 -06:00
Ross Thompson
fb3207fc72
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 16:57:29 -06:00
Ross Thompson
8d33bf0b4a
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
David Harris
e33db012ba
Reinstated many arch f/d tests that had failed because of memfile issues
2022-01-05 22:44:10 +00:00
David Harris
31067c8e7d
Restored many of the arch32f and arch64d that had been failing because of memfile issues
2022-01-05 22:23:46 +00:00
David Harris
30c1ab5213
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-05 22:10:33 +00:00
David Harris
355efda9bc
Replaced exe2memfile with SiFive elf2hex
2022-01-05 22:10:26 +00:00
Ross Thompson
75788dd9c2
Changes to wave file.
2022-01-05 14:16:59 -06:00
Ross Thompson
bd901cd125
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 14:15:27 -06:00
Ross Thompson
49eea2add5
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
David Harris
85fa620cfb
Finished removing generate statements
2022-01-05 16:41:17 +00:00
David Harris
32590d484c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
f04856ee94
Removed more generate statements
2022-01-05 16:01:03 +00:00
David Harris
c1d6550ccb
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
f89c1d91dc
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
9eda7c12bd
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
b06c3b8acd
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
06168e67e4
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
Ross Thompson
d94a1c6404
Fixed bug where last line of dcache was not written back to memory on dcache flush.
2022-01-04 21:55:48 -06:00
Ross Thompson
0dd61a57da
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-04 18:41:52 -06:00
Ross Thompson
3c3c6d0fe8
Fixed dcache flush.
2022-01-04 18:40:58 -06:00
David Harris
08e6a10480
Removed imperas mmu tests; using wallypriv instead
2022-01-04 23:14:53 +00:00
Kip Macsai-Goren
87ba45ce36
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 21:30:51 +00:00
Kip Macsai-Goren
0ee4e03cd6
fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh.
2022-01-04 21:30:38 +00:00
David Harris
57daff45c8
Fixed bad address for F/fmsub_b18-01
2022-01-04 21:04:06 +00:00
David Harris
1f07470477
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
