mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed PMA regions, Added passing PMA tests to regression
This commit is contained in:
Kip Macsai-Goren
parent
0b3d3b768b
commit
c251144460
@ -1475,8 +1475,8 @@ string imperas32f[] = '{
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`WALLYTEST,
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"rv64i_m/privilege/WALLY-MMU-SV39", "30A0",
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"rv64i_m/privilege/WALLY-MMU-SV48", "30A0",
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"rv64i_m/privilege/WALLY-PMP", "30A0"
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// "rv64i_m/privilege/WALLY-PMA", "30A0",
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"rv64i_m/privilege/WALLY-PMP", "30A0",
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"rv64i_m/privilege/WALLY-PMA", "30A0"
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};
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string wally64periph[] = '{
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@ -1491,8 +1491,8 @@ string wally32i[] = '{
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string wally32priv[] = '{
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`WALLYTEST,
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"rv32i_m/privilege/WALLY-MMU-SV32", "3080",
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"rv32i_m/privilege/WALLY-PMP", "3080"
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// "rv32i_m/privilege/WALLY-PMA", "3080"
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"rv32i_m/privilege/WALLY-PMP", "3080",
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"rv32i_m/privilege/WALLY-PMA", "3080"
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};
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string wally32periph[] = '{
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@ -1,13 +1,9 @@
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beef00b4
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beef00b5
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000000b6
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000000b7
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ffffffb7
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00000001
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00000bad
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00000007
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00000005
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00000bad
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beef00b9
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00000002
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00000007
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00000005
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00000bad
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@ -22,15 +18,9 @@ beef00b9
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00000007
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00000005
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00000bad
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00000007
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00000005
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00000bad
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000000bf
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ffffffbf
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00000001
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00000bad
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00000007
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00000005
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00000bad
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beef00c1
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00000007
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00000005
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@ -40,27 +30,37 @@ beef00c1
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00000bad
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00000001
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00000bad
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beef00c4
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000000c5
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000000c6
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00000007
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00000005
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00000bad
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00000001
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00000bad
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00000009
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deadbeef
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deadbeef
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deadbeef
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deadbeef
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deadbeef
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deadbeef
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deadbeef
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deadbeef
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deadbeef
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deadbeef
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deadbeef
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deadbeef
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00000007
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00000005
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00000bad
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00000001
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00000bad
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00000007
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00000005
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00000bad
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00000001
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00000bad
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00000007
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00000005
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00000bad
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00000001
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00000bad
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00000007
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00000005
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00000bad
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00000001
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00000bad
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00000007
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00000005
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00000bad
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00000001
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00000bad
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0000000b
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deadbeef
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deadbeef
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deadbeef
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@ -21,6 +21,19 @@
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#define BOOTROM_BASE 0x00001000
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#define BOOTROM_RANGE 0x00000FFF
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#define RAM_BASE 0x80000000
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#define RAM_RANGE 0x7FFFFFFF
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#define CLINT_BASE 0x02000000
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#define CLINT_RANGE 0x0000FFFF
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#define GPIO_BASE 0x10012000
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#define GPIO_RANGE 0x000000FF
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#define UART_BASE 0x10000000
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#define UART_RANGE 0x00000007
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#define PLIC_BASE 0x0C000000
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#define PLIC_RANGE 0x03FFFFFF
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#include "WALLY-TEST-LIB-32.S"
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// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions
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// Ideally this should mean that a test can be written by simply adding .4byte statements as below.
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@ -48,92 +61,92 @@
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# | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO |
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# | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO |
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# | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO |
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# | DRAM | 0x80000000 | Any | YES | YES | YES | YES | YES | YES |
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# ************** Cacheable, Idempotent, Atomic tests are not implemented yet.
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# ----------------- ROM ---------------------
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# *** the rom is read only and these read tests depend on reading a known value out of memory.
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# Is there some guaranteed value that I can read out of the ROM
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# otherwise the read test can be modified to just check that the read happened,
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# not necessarily that it got a known value out of memory. This feels hacky and Id be interested in other options.
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# ROM goes untested because it isn't writeable and these tests rely on writing a known value to memory.
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# .4byte 0x1000, 0xBEEF0001, 0x0 # 32-bit write: store access fault
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# .4byte 0x1000, 0xBEEF0001, 0x1 # 32-bit read: success
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# .4byte 0x1000, 0xBEEF0002, 0x12 # 16-bit write: store access fault
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# .4byte 0x1000, 0xBEEF0002, 0x15 # 16-bit read: success
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# .4byte 0x1000, 0xBEEF0003, 0x13 # 08-bit write: store access fault
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# .4byte 0x1000, 0xBEEF0003, 0x16 # 08-bit read: success
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# # *** similar problem with the execute tests. Impossible to write the needed executable code into rom once the program's running
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# .4byte 0x1000, 0x111, 0x2 # execute: success
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# ----------------- CLINT ---------------------
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.4byte 0x2000000, 0xBEEF00B5, 0x0 # 32-bit write: success
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.4byte 0x2000000, 0xBEEF00B5, 0x1 # 32-bit read: success
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.4byte 0x2000000, 0xBEEF00B6, 0x12 # 16-bit write: success
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.4byte 0x2000000, 0xBEEF00B6, 0x15 # 16-bit read: success
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.4byte 0x2000000, 0xBEEF00B7, 0x13 # 08-bit write: success
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.4byte 0x2000000, 0xBEEF00B7, 0x16 # 08-bit read: success
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# Use timecmp register as readable and writable section of the CLINT
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.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, 0x0 # 32-bit write: success
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.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, 0x1 # 32-bit read: success
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.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, 0x12 # 16-bit write: success
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.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, 0x15 # 16-bit read: success
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.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, 0x13 # 08-bit write: success
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.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, 0x16 # 08-bit read: success
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.4byte 0x2000000, 0xbad, 0x2 # execute: instruction access fault
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.4byte CLINT_BASE, 0xbad, 0x2 # execute: instruction access fault
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# ----------------- PLIC ---------------------
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.4byte 0xC000000, 0xBEEF00B9, 0x0 # 32-bit write: success
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.4byte 0xC000000, 0xBEEF00B9, 0x1 # 32-bit read: success
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.4byte 0xC000000, 0xBEEF00BA, 0x12 # 16-bit write: store access fault
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.4byte 0xC000000, 0xBEEF00BA, 0x15 # 16-bit read: load access fault
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.4byte 0xC000000, 0xBEEF00BB, 0x13 # 08-bit write: store access fault
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.4byte 0xC000000, 0xBEEF00BB, 0x16 # 08-bit read: load access fault
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# Write 0x2 instead of wider value to plic address because the register width might change.
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.4byte PLIC_BASE + 0x2000, 0x2, 0x0 # 32-bit write: success
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.4byte PLIC_BASE + 0x2000, 0x2, 0x1 # 32-bit read: success
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.4byte PLIC_BASE, 0xBEEF00BA, 0x12 # 16-bit write: store access fault
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.4byte PLIC_BASE, 0xBEEF00BA, 0x15 # 16-bit read: load access fault
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.4byte PLIC_BASE, 0xBEEF00BB, 0x13 # 08-bit write: store access fault
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.4byte PLIC_BASE, 0xBEEF00BB, 0x16 # 08-bit read: load access fault
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.4byte 0xC000000, 0xbad, 0x2 # execute: instruction access fault
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.4byte PLIC_BASE, 0xbad, 0x2 # execute: instruction access fault
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# ----------------- UART0 ---------------------
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.4byte 0x10000000, 0xBEEF00BD, 0x0 # 32-bit write: store access fault
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.4byte 0x10000000, 0xBEEF00BD, 0x1 # 32-bit read: load access fault
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.4byte 0x10000000, 0xBEEF00BE, 0x12 # 16-bit write: store access fault
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.4byte 0x10000000, 0xBEEF00BE, 0x15 # 16-bit read: load access fault
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.4byte 0x10000000, 0xBEEF00BF, 0x13 # 08-bit write: success
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.4byte 0x10000000, 0xBEEF00BF, 0x16 # 08-bit read: success
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.4byte UART_BASE, 0xBEEF00BD, 0x0 # 32-bit write: store access fault
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.4byte UART_BASE, 0xBEEF00BD, 0x1 # 32-bit read: load access fault
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.4byte UART_BASE, 0xBEEF00BE, 0x12 # 16-bit write: store access fault
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.4byte UART_BASE, 0xBEEF00BE, 0x15 # 16-bit read: load access fault
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# Different address for this test so that we write into a writable register in the uart.
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.4byte UART_BASE + 0x3, 0xBEEF00BF, 0x13 # 08-bit write: success
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.4byte UART_BASE + 0x3, 0xBEEF00BF, 0x16 # 08-bit read: success
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.4byte 0x10000000, 0xbad, 0x2 # execute: instruction access fault
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.4byte UART_BASE, 0xbad, 0x2 # execute: instruction access fault
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# ----------------- GPIO ---------------------
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.4byte 0x1012000, 0xBEEF00C1, 0x0 # 32-bit write: success
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.4byte 0x1012000, 0xBEEF00C1, 0x1 # 32-bit read: success
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.4byte 0x1012000, 0xBEEF00C2, 0x12 # 16-bit write: store access fault
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.4byte 0x1012000, 0xBEEF00C2, 0x15 # 16-bit read: load access fault
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.4byte 0x1012000, 0xBEEF00C3, 0x13 # 08-bit write: store access fault
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.4byte 0x1012000, 0xBEEF00C3, 0x16 # 08-bit read: load access fault
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.4byte GPIO_BASE + 0x8, 0xBEEF00C1, 0x0 # 32-bit write: success
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.4byte GPIO_BASE + 0x8, 0xBEEF00C1, 0x1 # 32-bit read: success
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.4byte GPIO_BASE, 0xBEEF00C2, 0x12 # 16-bit write: store access fault
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.4byte GPIO_BASE, 0xBEEF00C2, 0x15 # 16-bit read: load access fault
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.4byte GPIO_BASE, 0xBEEF00C3, 0x13 # 08-bit write: store access fault
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.4byte GPIO_BASE, 0xBEEF00C3, 0x16 # 08-bit read: load access fault
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.4byte 0x1012000, 0xbad, 0x2 # execute: instruction access fault
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.4byte GPIO_BASE, 0xbad, 0x2 # execute: instruction access fault
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# ----------------- DRAM ---------------------
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# the following is already tested by the fact that this test runs without error:
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# 32 bit reads and writes into DRAM,
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# Execution in DRAM
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# offset by 0xf000 to avoid overwriting the program
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.4byte 0x8000F000, 0xBEEF00C5, 0x12 # 16-bit write: success
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.4byte 0x8000F000, 0xBEEF00C5, 0x15 # 16-bit read: success
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.4byte 0x8000F000, 0xBEEF00C6, 0x13 # 08-bit write: success
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.4byte 0x8000F000, 0xBEEF00C6, 0x16 # 08-bit read: success
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# ----------------- Inaccessible ---------------------
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# show that load, store, and jalr cause faults in a region not defined by PMAs.
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# *** should I go through every possible inaccessible region of memory or is one just fine?
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.4byte 0xD000000, 0xBEEF00C7, 0x0 # 32-bit write: store access fault
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.4byte 0xD000000, 0xBEEF00C7, 0x1 # 32-bit read: load access fault
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.4byte 0x1000, 0x111, 0x2 # execute: instruction access fault
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# Tests 'random' place in unimplemented memory
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.4byte 0x40000000, 0xBEEF00C7, 0x0 # 32-bit write: store access fault
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.4byte 0x40000000, 0xBEEF00C7, 0x1 # 32-bit read: load access fault
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.4byte 0x40000000, 0x111, 0x2 # execute: instruction access fault
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.4byte 0x0, 0x0, 0x3 // terminate tests
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# Tests just past the end of each peripheral
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.4byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0xBEEF00C8, 0x0 # 32-bit write: store access fault
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.4byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0xBEEF00C8, 0x1 # 32-bit read: load access fault
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.4byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x111, 0x2 # execute: instruction access fault
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.4byte (CLINT_BASE+CLINT_RANGE+1), 0xBEEF00C9, 0x0 # 32-bit write: store access fault
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.4byte (CLINT_BASE+CLINT_RANGE+1), 0xBEEF00C9, 0x1 # 32-bit read: load access fault
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.4byte (CLINT_BASE+CLINT_RANGE+1), 0x111, 0x2 # execute: instruction access fault
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.4byte (PLIC_BASE+PLIC_RANGE+1), 0xBEEF00CA, 0x0 # 32-bit write: store access fault
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.4byte (PLIC_BASE+PLIC_RANGE+1), 0xBEEF00CA, 0x1 # 32-bit read: load access fault
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.4byte (PLIC_BASE+PLIC_RANGE+1), 0x111, 0x2 # execute: instruction access fault
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.4byte (UART_BASE+UART_RANGE+1), 0xBEEF00CB, 0x13 # 08-bit write: store access fault
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.4byte (UART_BASE+UART_RANGE+1), 0xBEEF00CB, 0x16 # 08-bit read: load access fault
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.4byte (UART_BASE+UART_RANGE+1), 0x111, 0x2 # execute: instruction access fault
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.4byte (GPIO_BASE+GPIO_RANGE+1), 0xBEEF00CC, 0x0 # 32-bit write: store access fault
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.4byte (GPIO_BASE+GPIO_RANGE+1), 0xBEEF00CC, 0x1 # 32-bit read: load access fault
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.4byte (GPIO_BASE+GPIO_RANGE+1), 0x111, 0x2 # execute: instruction access fault
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.4byte 0x0, 0x0, 0x3 # terminate tests
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@ -1,11 +1,11 @@
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beef00b4
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0000dead
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beef00b5
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00000000
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ffffffff
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000000b6
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00000000
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000000b7
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00000000
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ffffffb7
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ffffffff
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00000001
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00000000
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00000bad
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@ -16,7 +16,7 @@ beef00b5
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00000000
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00000bad
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00000000
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beef00b9
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00000002
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00000000
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00000007
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00000000
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@ -52,8 +52,8 @@ beef00b9
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00000000
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00000bad
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00000000
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000000bf
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00000000
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ffffffbf
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ffffffff
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00000001
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00000000
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00000bad
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@ -65,7 +65,7 @@ beef00b9
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00000bad
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00000000
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beef00c1
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00000000
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ffffffff
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00000007
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00000000
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00000005
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@ -21,7 +21,7 @@
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#define BOOTROM_BASE 0x00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
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#define BOOTROM_BASE 0x00001000
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#define BOOTROM_RANGE 0x00000FFF
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#define RAM_BASE 0x80000000
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#define RAM_RANGE 0x7FFFFFFF
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@ -70,88 +70,90 @@
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# ----------------- CLINT ---------------------
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.8byte CLINT_BASE, 0xEEEEEEEEEEEEEEEE, 0x0 # 64-bit write: success
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.8byte CLINT_BASE, 0x0000DEADBEEF00B4, 0x1 # 64-bit read: success
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.8byte CLINT_BASE, 0x0000DEADBEEF00B5, 0x11 # 32-bit write: success
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.8byte CLINT_BASE, 0x0000DEADBEEF00B5, 0x14 # 32-bit read: success
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.8byte CLINT_BASE, 0x0000DEADBEEF00B6, 0x12 # 16-bit write: success
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.8byte CLINT_BASE, 0x0000DEADBEEF00B6, 0x15 # 16-bit read: success
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.8byte CLINT_BASE, 0x0000DEADBEEF00B7, 0x13 # 08-bit write: success
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.8byte CLINT_BASE, 0x0000DEADBEEF00B7, 0x16 # 08-bit read: success
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# Use timecmp register as readable and writable section of the CLINT
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.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, 0x0 # 64-bit write: success
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.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, 0x1 # 64-bit read: success
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.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, 0x11 # 32-bit write: success
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.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, 0x14 # 32-bit read: success
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.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, 0x12 # 16-bit write: success
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.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, 0x15 # 16-bit read: success
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.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, 0x13 # 08-bit write: success
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.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, 0x16 # 08-bit read: success
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.8byte CLINT_BASE, 0xbad, 0x2 # execute: instruction access fault
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.8byte CLINT_BASE, 0xbad, 0x2 # execute: instruction access fault
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# ----------------- PLIC ---------------------
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.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x0 # 64-bit write: store access fault
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.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x1 # 64-bit read: load access fault
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.8byte PLIC_BASE, 0x0000DEADBEEF00B9, 0x11 # 32-bit write: success
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.8byte PLIC_BASE, 0x0000DEADBEEF00B9, 0x14 # 32-bit read: success
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.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x12 # 16-bit write: store access fault
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.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x15 # 16-bit read: load access fault
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.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x13 # 08-bit write: store access fault
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.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x16 # 08-bit read: load access fault
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.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x0 # 64-bit write: store access fault
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.8byte PLIC_BASE, 0x0000DEADBEEF00B8, 0x1 # 64-bit read: load access fault
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# Write 0x2 instead of wider value to plic address because the register width might change.
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||||
.8byte PLIC_BASE + 0x2000, 0x2, 0x11 # 32-bit write: success
|
||||
.8byte PLIC_BASE + 0x2000, 0x2, 0x14 # 32-bit read: success
|
||||
.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x12 # 16-bit write: store access fault
|
||||
.8byte PLIC_BASE, 0x0000DEADBEEF00BA, 0x15 # 16-bit read: load access fault
|
||||
.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x13 # 08-bit write: store access fault
|
||||
.8byte PLIC_BASE, 0x0000DEADBEEF00BB, 0x16 # 08-bit read: load access fault
|
||||
|
||||
.8byte PLIC_BASE, 0xbad, 0x2 # execute: instruction access fault
|
||||
.8byte PLIC_BASE, 0xbad, 0x2 # execute: instruction access fault
|
||||
|
||||
# ----------------- UART0 ---------------------
|
||||
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x0 # 64-bit write: store access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x1 # 64-bit read: load access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x11 # 32-bit write: store access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x14 # 32-bit read: load access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x12 # 16-bit write: store access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x15 # 16-bit read: load access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BF, 0x13 # 08-bit write: success
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BF, 0x16 # 08-bit read: success
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x0 # 64-bit write: store access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BC, 0x1 # 64-bit read: load access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x11 # 32-bit write: store access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BD, 0x14 # 32-bit read: load access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x12 # 16-bit write: store access fault
|
||||
.8byte UART_BASE, 0x0000DEADBEEF00BE, 0x15 # 16-bit read: load access fault
|
||||
# Different address for this test so that we write into a writable register in the uart.
|
||||
.8byte UART_BASE + 0x3, 0x0000DEADBEEF00BF, 0x13 # 08-bit write: success
|
||||
.8byte UART_BASE + 0x3, 0x0000DEADBEEF00BF, 0x16 # 08-bit read: success
|
||||
|
||||
.8byte UART_BASE, 0xbad, 0x2 # execute: instruction access fault
|
||||
.8byte UART_BASE, 0xbad, 0x2 # execute: instruction access fault
|
||||
|
||||
# ----------------- GPIO ---------------------
|
||||
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x0 # 64-bit write: store access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x1 # 64-bit read: load access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C1, 0x11 # 32-bit write: success
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C1, 0x14 # 32-bit read: success
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x12 # 16-bit write: store access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x15 # 16-bit read: load access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x13 # 08-bit write: store access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x16 # 08-bit read: load access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x0 # 64-bit write: store access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C0, 0x1 # 64-bit read: load access fault
|
||||
.8byte GPIO_BASE + 0x8, 0x0000DEADBEEF00C1, 0x11 # 32-bit write: success
|
||||
.8byte GPIO_BASE + 0x8, 0x0000DEADBEEF00C1, 0x14 # 32-bit read: success
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x12 # 16-bit write: store access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C2, 0x15 # 16-bit read: load access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x13 # 08-bit write: store access fault
|
||||
.8byte GPIO_BASE, 0x0000DEADBEEF00C3, 0x16 # 08-bit read: load access fault
|
||||
|
||||
.8byte GPIO_BASE, 0xbad, 0x2 # execute: instruction access fault
|
||||
.8byte GPIO_BASE, 0xbad, 0x2 # execute: instruction access fault
|
||||
|
||||
# ----------------- Inaccessible ---------------------
|
||||
|
||||
# show that load, store, and jalr cause faults in a region not defined by PMAs.
|
||||
# *** should I go through every possible inaccessible region of memory or is one just fine?
|
||||
# show that load, store, and jalr cause faults in regions not defined by PMAs.
|
||||
|
||||
# Tests 'random' place in unimplemented memory
|
||||
.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault
|
||||
.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault
|
||||
.8byte 0xD000000, 0x111, 0x2 # execute: instruction access fault
|
||||
.8byte 0x40000000, 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault
|
||||
.8byte 0x40000000, 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault
|
||||
.8byte 0x40000000, 0x111, 0x2 # execute: instruction access fault
|
||||
|
||||
# Tests just past the end of each peripheral
|
||||
.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault
|
||||
.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault
|
||||
.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C8, 0x0 # 64-bit write: store access fault
|
||||
.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x0000DEADBEEF00C8, 0x1 # 64-bit read: load access fault
|
||||
.8byte (BOOTROM_BASE+BOOTROM_RANGE+1), 0x111, 0x2 # execute: instruction access fault
|
||||
|
||||
.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault
|
||||
.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault
|
||||
.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C9, 0x0 # 64-bit write: store access fault
|
||||
.8byte (CLINT_BASE+CLINT_RANGE+1), 0x0000DEADBEEF00C9, 0x1 # 64-bit read: load access fault
|
||||
.8byte (CLINT_BASE+CLINT_RANGE+1), 0x111, 0x2 # execute: instruction access fault
|
||||
|
||||
.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00C7, 0x11 # 32-bit write: store access fault
|
||||
.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00C7, 0x14 # 32-bit read: load access fault
|
||||
.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00CA, 0x11 # 32-bit write: store access fault
|
||||
.8byte (PLIC_BASE+PLIC_RANGE+1), 0x0000DEADBEEF00CA, 0x14 # 32-bit read: load access fault
|
||||
.8byte (PLIC_BASE+PLIC_RANGE+1), 0x111, 0x2 # execute: instruction access fault
|
||||
|
||||
.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00C7, 0x13 # 08-bit write: store access fault
|
||||
.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00C7, 0x16 # 08-bit read: load access fault
|
||||
.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00CB, 0x13 # 08-bit write: store access fault
|
||||
.8byte (UART_BASE+UART_RANGE+1), 0x0000DEADBEEF00CB, 0x16 # 08-bit read: load access fault
|
||||
.8byte (UART_BASE+UART_RANGE+1), 0x111, 0x2 # execute: instruction access fault
|
||||
|
||||
.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00C7, 0x11 # 32-bit write: store access fault
|
||||
.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00C7, 0x14 # 32-bit read: load access fault
|
||||
.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00CC, 0x11 # 32-bit write: store access fault
|
||||
.8byte (GPIO_BASE+GPIO_RANGE+1), 0x0000DEADBEEF00CC, 0x14 # 32-bit read: load access fault
|
||||
.8byte (GPIO_BASE+GPIO_RANGE+1), 0x111, 0x2 # execute: instruction access fault
|
||||
|
||||
.8byte 0x0, 0x0, 0x3 // terminate tests
|
||||
.8byte 0x0, 0x0, 0x3 # terminate tests
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user