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https://github.com/openhwgroup/cvw
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BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush.
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@ -334,7 +334,6 @@ module ifu (
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(PCBPWrongInvalidate));
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mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
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flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), .d(BPPredWrongE), .q(BPPredWrongM));
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assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
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@ -344,6 +343,8 @@ module ifu (
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if (`BPRED_ENABLED) begin : bpred
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logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), .d(BPPredWrongE), .q(BPPredWrongM));
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bpred bpred(.clk, .reset,
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.StallF, .StallD, .StallE,
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.FlushF, .FlushD, .FlushE,
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@ -369,6 +370,7 @@ module ifu (
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end else begin : bpred
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assign BPPredPCF = '0;
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assign BPPredWrongE = PCSrcE;
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assign BPPredWrongM = '0;
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assign {SelBPPredF, BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
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end
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