David Harris
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c60bb68bff
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Testgen working for Lab 2
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2022-01-26 18:01:51 +00:00 |
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David Harris
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492c1a488e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-26 17:21:09 +00:00 |
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David Harris
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f90e58ff34
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New testgen.py
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2022-01-26 17:21:02 +00:00 |
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bbracker
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ea92cc3af2
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a different approach to QEMU: add Wally as a completely new machine
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2022-01-26 15:02:24 +00:00 |
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Ross Thompson
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728e46a794
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-25 19:21:04 -06:00 |
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Ross Thompson
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db197b6491
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Added pin location for reset on VCU118 board. Somehow this was missing and still worked.
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2022-01-25 17:48:42 -06:00 |
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David Harris
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1e533cdf25
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Removed and restored embench-iot
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2022-01-25 22:12:28 +00:00 |
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Ross Thompson
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71eb1df492
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Added comport.setup to remind how to configure com port for xilinx fpga.
Added load-deadlock.tsm to trigger load operation deadlock.
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2022-01-25 14:54:38 -06:00 |
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David Harris
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22c84dcd80
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simpleram simplification
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2022-01-25 19:46:13 +00:00 |
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David Harris
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8bf73d0eb3
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simpleram simplification
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2022-01-25 19:40:07 +00:00 |
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David Harris
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f07123ff0f
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simpleram simplification
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2022-01-25 18:26:31 +00:00 |
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David Harris
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7ac44cb3fc
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simpleram address simplification
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2022-01-25 18:17:33 +00:00 |
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David Harris
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5eb71a3bbe
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simpleram address simplification
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2022-01-25 18:00:50 +00:00 |
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David Harris
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d9888c91a6
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simpleram clk and reset simplification
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2022-01-25 17:34:15 +00:00 |
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David Harris
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5cb879129e
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Start of IFU cleanup
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2022-01-25 17:31:53 +00:00 |
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David Harris
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0660e5fe51
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removed sum executable
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2022-01-25 10:24:05 +00:00 |
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David Harris
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44c58cfa20
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-25 06:53:07 +00:00 |
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David Harris
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4c8c359894
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More example Makefile cleanup
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2022-01-25 06:53:03 +00:00 |
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davidharrishmc
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6fa63bf6d7
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Update README.md
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2022-01-24 15:47:42 -08:00 |
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davidharrishmc
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edff52c692
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Update README.md
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2022-01-24 15:46:24 -08:00 |
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David Harris
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96e9cd6ef1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-24 23:21:16 +00:00 |
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David Harris
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26013a984b
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Fixed sumtest reference output; added embench benchmark directory
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2022-01-24 23:21:09 +00:00 |
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kaveh Pezeshki
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3314fb48c4
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added qemu patches in tests/linux-testgen/qemu
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2022-01-24 07:52:07 +00:00 |
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Ross Thompson
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4d4d9ac8cf
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Added spill support back into the IROM IFU.
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2022-01-21 15:50:54 -06:00 |
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Ross Thompson
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4ecc2d029a
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Changed the IROM and DTIM memories to behave like edge-triggered srams.
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2022-01-21 15:42:54 -06:00 |
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David Harris
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c2c7351b24
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erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-21 00:12:18 +00:00 |
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David Harris
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0bb63e9ad1
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Fixed path to riscvOVPsimPlus
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2022-01-21 00:12:14 +00:00 |
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Ross Thompson
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ec44774c77
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Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
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2022-01-20 16:39:54 -06:00 |
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David Harris
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d1162eeebf
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fir.c
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2022-01-20 17:15:53 +00:00 |
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David Harris
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ac28880cd9
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Added FIR example
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2022-01-20 16:57:36 +00:00 |
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David Harris
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ca1f7ce5d3
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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David Harris
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0d0aa59e48
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Removed imperas tests from makefile for now
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2022-01-20 14:51:56 +00:00 |
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David Harris
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f420e63ed0
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Added top-level make clean
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2022-01-20 14:17:26 +00:00 |
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David Harris
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537cb1d1e1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-20 00:04:27 +00:00 |
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David Harris
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ab25aa4df9
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Created linux directory for linux config
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2022-01-20 00:04:23 +00:00 |
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Ross Thompson
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05ebadacad
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Added PCNextF and PostSpillInstrRawF to ila.
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2022-01-19 14:05:14 -06:00 |
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Ross Thompson
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305fccfe7a
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Fixed fpga ila debug to match lsu changes.
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2022-01-18 21:13:18 -06:00 |
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David Harris
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f966d98e56
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-19 00:26:34 +00:00 |
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Ross Thompson
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5cf686429d
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Merged in the debug ila updates.
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2022-01-18 17:29:21 -06:00 |
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Ross Thompson
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2508b9d35a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-18 17:19:59 -06:00 |
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Ross Thompson
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fdc17f5017
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Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
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2022-01-18 17:19:33 -06:00 |
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David Harris
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1a21e7f011
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riscvsingle reparittioned to match Ch4
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2022-01-17 16:57:32 +00:00 |
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David Harris
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de7b9c127e
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Added E extension, and downloaded riscv-dv and embench-iot to addins
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2022-01-17 14:42:59 +00:00 |
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David Harris
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5842d780a7
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Defined rv32e and rv32emc configs
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2022-01-17 14:01:01 +00:00 |
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David Harris
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8b62130070
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lsu cleanup down to 346 lines
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2022-01-15 01:19:44 +00:00 |
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David Harris
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b967bcede2
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LSU Cleanup
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2022-01-15 01:11:17 +00:00 |
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David Harris
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f7f3882cb8
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Moved Dcache into bus block
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2022-01-15 00:39:07 +00:00 |
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David Harris
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d9e8d16bbe
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Renamed LSUStall to LSUStallM
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2022-01-15 00:24:16 +00:00 |
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David Harris
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b0263012e8
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LSU cleanup
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2022-01-15 00:11:30 +00:00 |
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David Harris
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4c5962095e
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LSU cleanup
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2022-01-15 00:03:03 +00:00 |
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