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Configurable RISC-V Processor

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Ross Thompson 2508b9d35a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2022-01-18 17:19:59 -06:00
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benchmarks/riscv-coremark	Merged coremark changes	2022-01-10 05:09:28 +00:00
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examples	Mixed C and assembly language test cases; SRT initial version passing tests	2022-01-13 21:45:54 +00:00
fpga	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
pipelined	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-18 17:19:59 -06:00
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setup.sh	Code cleanup	2022-01-07 04:07:04 +00:00
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README.md

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

See Chapter 2 of draft book of how to install and compile tests.