631 Commits

Author	SHA1	Message	Date
David Harris	c5868b81e4	privileged cleanup	2022-05-12 20:21:33 +00:00
mmasserfrye	517e44746e	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-12 20:20:40 +00:00
mmasserfrye	2675c217e0	cleaned lint for ppa.sv	2022-05-12 20:20:05 +00:00
David Harris	5537c33196	Formatting cleanup	2022-05-12 18:37:47 +00:00
mmasserfrye	57a69d0f67	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-12 18:08:20 +00:00
mmasserfrye	30a1ba7bcf	renamed madzscript, modified ppa.sv alu and shifter	2022-05-12 18:05:02 +00:00
David Harris	449472ba58	Moved Breakpoint and Ecall fault logic into privdec	2022-05-12 16:45:53 +00:00
David Harris	9f8dca5190	Moved TLB Flush logic into privdec	2022-05-12 16:41:52 +00:00
David Harris	1d01bc98a4	Moved WFI timeout into privdec	2022-05-12 16:22:39 +00:00
David Harris	21c1e58829	Partitioned privilege mode fsm into new module	2022-05-12 16:16:42 +00:00
David Harris	61199ccd13	More signal cleanup	2022-05-12 15:39:44 +00:00
David Harris	4c5e361b00	More unused signal cleanup	2022-05-12 15:26:08 +00:00
David Harris	5acb526375	More unused signal cleanup	2022-05-12 15:21:09 +00:00
David Harris	7e764fbda1	More unused signal cleanup	2022-05-12 15:15:30 +00:00
David Harris	e2dea3bb89	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	fb725a9e0a	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	8372bc86a7	Removing unused signals	2022-05-12 14:36:15 +00:00
David Harris	15659b05e4	Simplifed mstatus.TSR handling	2022-05-12 14:09:52 +00:00
David Harris	877c4eefd1	Fixed typo in csrm	2022-05-12 06:55:39 -07:00
mmasserfrye	cf900cf44d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-12 07:24:04 +00:00
mmasserfrye	52b0e7d567	filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv	2022-05-12 07:22:06 +00:00
David Harris	32f8841f79	Added MCONFIGPTR CSR hardwired to 0	2022-05-12 04:31:45 +00:00
David Harris	c738c130de	merged ppa.sv	2022-05-11 18:14:16 +00:00
David Harris	e37d262e4c	PPA script progress	2022-05-11 18:11:51 +00:00
mmasserfrye	70fe1184db	ed ... modified ppa.sv	2022-05-11 16:22:12 +00:00
David Harris	a8c9f504fa	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	91472eb948	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	91b786c58d	Updated PPA experiment	2022-05-10 23:09:42 +00:00
David Harris	d53e4b1b1f	Initial PPA study	2022-05-10 20:48:47 +00:00
David Harris	b869190161	endian swapper	2022-05-08 06:51:50 +00:00
David Harris	8066ba45e8	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	2792d77e4e	Fixed bug in delegated interrupts not being taken	2022-05-08 04:50:27 +00:00
David Harris	2cdd49c7d2	WFI terminates when an interrupt is pending even if interrupts are globally disabled	2022-05-08 04:30:46 +00:00
David Harris	7024293a59	Zero'd wfiM when ZICSR not supported to fix hang in E tests	2022-05-05 15:32:13 +00:00
David Harris	66424a8246	SFENCE.VMA should be illegal in user mode	2022-05-05 15:15:02 +00:00
David Harris	866540580a	SFENCE.VMA should be illegal in user mode	2022-05-05 14:59:52 +00:00
David Harris	c100c9893b	wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts	2022-05-05 14:37:21 +00:00
David Harris	94459ade3d	Changed WFI to stall pipeline in memory stage	2022-05-05 02:03:44 +00:00
Kip Macsai-Goren	25ad39939f	put privileged tests back into rv32/64gc	2022-05-04 21:20:25 +00:00
Kip Macsai-Goren	0f70e48b6b	updated makefrag and tests.vh to reflect removed tests, new names	2022-05-04 21:20:25 +00:00
David Harris	8eee0c0ca3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-03 18:32:04 +00:00
David Harris	554c2b3550	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
David Harris	cb1a7d54a4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-05-03 08:53:35 -07:00
David Harris	4fbf78e049	clean up sram1p1rw; still doesn't work on Modelsim 2022.1	2022-05-03 08:31:54 -07:00
David Harris	9c4de0e9c1	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
David Harris	dee32f70bf	Switched to behavioral comparator for best PPA	2022-05-03 11:00:39 +00:00
David Harris	bc123b5564	Comparator experiments	2022-05-03 10:54:30 +00:00
David Harris	7e3f75a35d	Formatting cache.sv	2022-05-03 10:53:20 +00:00
David Harris	bc132c3e20	sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera	2022-05-03 03:50:41 -07:00
David Harris	3f2ec0499f	Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.	2022-05-03 03:45:41 -07:00