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250 Commits

Author SHA1 Message Date
Daniel Torres
8dcb794bbb added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
Daniel Torres
9421b77613 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-21 12:50:04 -07:00
Daniel Torres
a8faddf81f removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
Katherine Parry
fbe8bb2298 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Katherine Parry
7950a675ea added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
Daniel Torres
5b1adc7a67 commented out embench 2.0 tests 2022-07-19 13:36:18 -07:00
Katherine Parry
514674417e moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
cce5fb8dfd moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
7268b4b334 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
0210718f19 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
Katherine Parry
5cb9c9f319 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
Katherine Parry
2fe8b6e34c fixed error in divsqrt 2022-07-14 18:16:00 +00:00
Katherine Parry
b874c5c05d removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
Katherine Parry
3c1bea1104 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
18d7fee541 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
ba339fc794 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
bea4ec078d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
DTowersM
fe7d03a3da added some preliminary support for coremark XLEN=32, made sure rv64 not impacted 2022-07-11 21:13:09 +00:00
Katherine Parry
62205ebb3b renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
97e7e619d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
Katherine Parry
c56fdd7e0f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
88b4f9b40a renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
David Harris
8be1dafbd6 Removed testbench code that ignores mismatch on zero signatures 2022-07-08 09:17:31 +00:00
DTowersM
4786fb9fd6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-07 23:11:35 +00:00
DTowersM
aa8580b2dc new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory 2022-07-07 23:11:02 +00:00
Katherine Parry
75a8cea4e4 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
David Harris
f865994ba1 fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
7771f7b3eb added load and store test 2022-07-07 21:48:51 +00:00
DTowersM
5dfff900b1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-06 23:44:27 +00:00
DTowersM
67c5d66209 added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu 2022-07-06 23:43:57 +00:00
David Harris
f5bdbbe219 Removed sig4 spurious message from testbench 2022-07-05 03:27:14 +00:00
Katherine Parry
2fc795ca70 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
8ac722f693 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
Daniel Torres
d1eebac73f reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished 2022-06-29 12:32:30 -07:00
Daniel Torres
2ae22ac6cb added changes to testbench, tests and riscof for additional riscof compatability 2022-06-29 12:23:40 -07:00
slmnemo
228028c837 Add CLINT tests from book 2022-06-27 20:09:58 -07:00
Katherine Parry
a5fb60eb1a radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
70a1bb8377 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
Katherine Parry
9eefba5b58 added denormal input handeling - radix 4 2022-06-24 19:41:40 +00:00
Katherine Parry
de71773d69 added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
Katherine Parry
a5fc6757a1 generate qsel4 in verilog 2022-06-23 21:38:04 +00:00
Katherine Parry
d7a363aaa7 fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
1612daa294 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
David Harris
d865a1ce95 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 22:45:28 +00:00
slmnemo
80a57d0469 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
b2cea45de0 Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
03d823f5d7 added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Daniel Torres
397783812d embench and testbench now support running both O2 and Os build variations without overwriting one another 2022-06-17 21:15:42 -07:00
Daniel Torres
1d4c543f71 arch tests now run on spike and sail and compare signatures during build 2022-06-17 20:53:15 -07:00
Daniel Torres
0ede7c412e removed old code from makefile, simplified code in testbench 2022-06-17 15:13:38 -07:00