David Harris
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c117356432
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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James E. Stine
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b36d6fe1be
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slight mod to fpdiv - still bug in batch vs. non-batch
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2021-07-20 01:47:46 -04:00 |
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Ross Thompson
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ae2371f2ce
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Added performance counters for dcache access and dcache miss.
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2021-07-19 22:12:20 -05:00 |
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Ross Thompson
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07c47f0034
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Restored TIM range.
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2021-07-19 21:17:31 -05:00 |
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bbracker
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a01fea69dd
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 19:30:40 -04:00 |
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bbracker
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af5d319f08
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change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole)
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2021-07-19 19:30:29 -04:00 |
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David Harris
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678f705415
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 18:19:59 -04:00 |
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David Harris
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b2f7952b3d
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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bbracker
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aeaf4a31f0
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MemRWM shouldn't factor into PCD checking
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2021-07-19 18:03:30 -04:00 |
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bbracker
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30c381c707
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create qemu_output.txt
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2021-07-19 18:02:41 -04:00 |
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bbracker
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45b78dd8b3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 17:11:49 -04:00 |
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bbracker
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5911029d2b
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make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
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2021-07-19 17:11:42 -04:00 |
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Kip Macsai-Goren
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3a73ae0a8b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 16:46:46 -04:00 |
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bbracker
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bb2e3b1e02
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remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux
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2021-07-19 16:22:05 -04:00 |
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bbracker
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78e513160e
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put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests
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2021-07-19 16:19:24 -04:00 |
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bbracker
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d603f4ea57
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 15:42:26 -04:00 |
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bbracker
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009e9d97bf
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adapt testbench to removal of ReadDataWEn signal
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2021-07-19 15:42:14 -04:00 |
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bbracker
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02de6014b2
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adapt testbench to removal of signal
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2021-07-19 15:41:50 -04:00 |
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bbracker
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76be84fa92
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whoops MTIMECMP is always 64 bits
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2021-07-19 15:40:53 -04:00 |
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kipmacsaigoren
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cbbfc2d3fc
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removed Wally test framwork include statement
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2021-07-19 19:15:11 +00:00 |
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bbracker
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fb6e618b1c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 15:13:14 -04:00 |
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bbracker
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77b690faf0
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make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
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2021-07-19 15:13:03 -04:00 |
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Kip Macsai-Goren
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c1c564d54c
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added changes to priority encoders from synthesis branch (correctly this time I hope)
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2021-07-19 15:06:14 -04:00 |
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Ross Thompson
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5edd513f8c
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Furture simplification of the dcache ReadDataW update.
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2021-07-19 12:46:31 -05:00 |
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Ross Thompson
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5754b5f25f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-19 12:32:35 -05:00 |
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Ross Thompson
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2ee97efb9c
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Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
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2021-07-19 12:32:16 -05:00 |
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bbracker
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8cbd83e804
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 13:21:04 -04:00 |
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bbracker
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2702064dda
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change buildroot expectations to match reality
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2021-07-19 13:20:53 -04:00 |
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Kip Macsai-Goren
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0c8a179c0b
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rename page table levels
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2021-07-19 13:00:59 -04:00 |
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Kip Macsai-Goren
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6f5e1b9d01
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 13:00:25 -04:00 |
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bbracker
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986b7a8252
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change sram1rw to have a small delay so that we don't have signals changing on clock edges
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2021-07-19 11:30:07 -04:00 |
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Kip Macsai-Goren
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f9fdd456bd
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 10:56:48 -04:00 |
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Kip Macsai-Goren
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9c7158bfc9
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Revert "added priority circuit to attempt to remove delay due to rippling in pmpadrdec"
This reverts commit 9461fd9fbd51e17a416a7df6982379fbfa6b0974.
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2021-07-19 10:46:17 -04:00 |
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David Harris
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1b55f584c7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 10:34:18 -04:00 |
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Kip Macsai-Goren
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704444a3c5
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added priority circuit to attempt to remove delay due to rippling in pmpadrdec
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2021-07-19 10:34:17 -04:00 |
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James Stine
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62b4ef6953
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delete sbtm_a4 and sbtm_a5 as they are not needed
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2021-07-19 08:06:00 -05:00 |
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James Stine
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892bc68918
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remove sbtm3.sv - not needed
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2021-07-19 08:00:53 -05:00 |
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James Stine
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55f2720f89
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update part I on sbtm change
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2021-07-19 07:59:27 -05:00 |
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David Harris
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0c41b8102d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 00:25:06 -04:00 |
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Katherine Parry
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8d101548f1
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FDIV and FSQRT passes when simulating in modelsim
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2021-07-18 23:00:04 -04:00 |
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bbracker
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f209cf0100
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-18 21:50:05 -04:00 |
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bbracker
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64a81941ff
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change memread testvectors to not left-shift bytes and half-words
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2021-07-18 21:49:53 -04:00 |
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David Harris
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4729a72167
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Updated FMA1 with parameterized size
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2021-07-18 20:40:49 -04:00 |
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James E. Stine
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26f146242e
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temp fpdivsqrt
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2021-07-18 20:04:18 -04:00 |
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bbracker
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f4f3ef0307
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linux testbench progress
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2021-07-18 18:47:40 -04:00 |
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David Harris
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398e9583e9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-18 17:36:29 -04:00 |
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David Harris
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f22b6e7397
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Added FLEN, NE, NF to config and started using these in FMA1
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2021-07-18 17:28:25 -04:00 |
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Katherine Parry
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3527620c0b
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fdivsqrt inegrated, but not completley working
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2021-07-18 14:03:37 -04:00 |
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David Harris
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e31d2ef9f5
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Renamed pagetablewalker to hptw
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2021-07-18 04:11:33 -04:00 |
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David Harris
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e962324d00
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LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall
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2021-07-18 03:51:30 -04:00 |
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