Ross Thompson
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bf69a2e1cd
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Updated to use the newest imperasDV.
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2024-07-09 12:30:18 -05:00 |
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Ross Thompson
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dc97ee5f82
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Have some sample code which I know works transmisting a packet.
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2024-07-02 09:12:34 -07:00 |
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Ross Thompson
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ccf4bb8ddc
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Maybe have the incircuit trigger working.
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2024-06-26 16:15:46 -07:00 |
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Ross Thompson
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612a281f62
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Added module to receive ethernet frame and trigger the ila.
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2024-06-26 11:05:31 -07:00 |
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Ross Thompson
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74189e1e4b
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Have vivado triggering the ILA after the mismatch but the latency is way too long.
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2024-06-25 17:04:14 -07:00 |
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Ross Thompson
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fa26c9a8b5
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Added pipe to vivado to create ila trigger from rvvidaemon.
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2024-06-25 13:07:46 -07:00 |
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Ross Thompson
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249d58244a
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It's working!!!!!!
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2024-06-20 15:48:30 -07:00 |
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Ross Thompson
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1c6ebb86a3
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Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
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2024-06-20 12:54:12 -07:00 |
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Ross Thompson
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93829ce509
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Success! We have some instructions comparing across the FPGA and IDV!
However I'm still losing ethernet frames.
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2024-06-17 13:41:40 -07:00 |
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Ross Thompson
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598770da51
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Getting much closer to a working version.
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2024-06-17 12:37:10 -07:00 |
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Ross Thompson
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82b54c0887
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Got IDV properly initalized.
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2024-06-17 09:15:59 -07:00 |
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Ross Thompson
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47523c97ac
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Getting closer to figuring out the lost ethernet frame bugs.
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2024-06-13 15:46:54 -07:00 |
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Ross Thompson
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c9f51df34a
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Fixed bug in rvvi reset.
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2024-06-12 14:47:32 -07:00 |
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Ross Thompson
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323dbd348e
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Progress.
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2024-06-12 12:54:21 -07:00 |
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Ross Thompson
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f5d4db68b1
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Modified rvvidaemon to populate a struct with all the relavent fields.
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2024-06-12 08:56:16 -07:00 |
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Ross Thompson
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3e7d07dfb6
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Better.
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2024-06-11 17:14:59 -07:00 |
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Ross Thompson
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8bce2fc739
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Getting closer.
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2024-06-11 16:21:53 -07:00 |
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Ross Thompson
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c9f3da51cb
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getting closer to full reconstruction of rvvi.
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2024-06-11 15:35:35 -07:00 |
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Ross Thompson
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3d9f796f21
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Better parsing of rvvi.
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2024-06-11 14:36:34 -07:00 |
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Ross Thompson
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563980443a
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Merge branch 'main' into rvvi
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2024-06-10 18:10:23 -07:00 |
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Ross Thompson
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49912589f5
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Added rvviApi.h to rvvidaemon.
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2024-06-10 17:57:24 -07:00 |
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Ross Thompson
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e16cf9d739
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Added Makefile to compile rvvidaemon
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2024-06-10 16:56:53 -07:00 |
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Rose Thompson
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72c1374d9c
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Minor code cleanup.
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2024-06-04 15:11:57 -05:00 |
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Rose Thompson
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f0ed780745
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progress.
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2024-06-04 15:11:03 -05:00 |
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Rose Thompson
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07d66c246c
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Update.
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2024-06-04 11:59:17 -05:00 |
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Rose Thompson
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08ff88f428
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On the way towards complete reconstruction of the RVVI trace.
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2024-06-04 11:47:46 -05:00 |
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Rose Thompson
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80f98b3223
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now have a working ethernet daemon to collect frames and partially decode into RVVI.
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2024-06-04 10:20:51 -05:00 |
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Jacob Pease
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7a417d7a6c
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Added true bootloader to fpga/zsbl directory.
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2024-05-31 15:28:25 -05:00 |
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Rose Thompson
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6a4c8667df
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Added new signals to ILA to debug the RVVI tracer.
The tracer appears to be stuck and the CPU is never getting out of (into reset).
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2024-05-30 16:43:25 -05:00 |
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Rose Thompson
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38ddbf860e
|
Fixed bug with mmcm not generating the 4th clock.
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2024-05-30 16:19:28 -05:00 |
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Jacob Pease
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3f7659c8ad
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Removed old fpgaTop.v file.
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2024-05-30 16:15:19 -05:00 |
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Jacob Pease
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7ecd1c7d5f
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The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
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2024-05-30 15:48:27 -05:00 |
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Rose Thompson
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9703055758
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The FPGA is synthesizing with the rvvi and ethernet hardware.
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2024-05-30 15:37:17 -05:00 |
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Rose Thompson
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8123695831
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Maded insert_debug_comment.sh compatible with cygwin.
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2024-04-22 10:48:34 -05:00 |
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Rose Thompson
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3bed733301
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Fixed fpga to work with the updated regression changes.
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2024-04-22 10:42:01 -05:00 |
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Rose Thompson
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c1221e6608
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Fixed insert_debug_comment.sh to work with the older version of bash.
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2024-04-16 10:55:26 -05:00 |
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Rose Thompson
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6097444b5a
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Added missing file for compiling the fpga zero stage bootloader.
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2024-04-11 10:30:56 -05:00 |
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Rose Thompson
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60f96112db
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Moved the zero stage boot loader to the fpga directory.
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2024-03-01 10:23:55 -06:00 |
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Rose Thompson
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cc7f433ce0
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Update the fpga scripts to use the new derivative configs.
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2024-01-31 13:19:28 -06:00 |
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David Harris
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45e2317636
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Added Wally github address to header comments
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2024-01-29 05:38:11 -08:00 |
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Rose Thompson
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7693c5d4e2
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Updates to fpga top level.
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2023-12-15 15:32:05 -06:00 |
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Rose Thompson
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26cd22c388
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Replaced fpga's verilog top with system verilog.
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2023-12-15 13:42:52 -06:00 |
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Rose Thompson
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dab9d7ab3c
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Replaced fpga top level verilog with system verilog.
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2023-12-15 13:07:08 -06:00 |
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Rose Thompson
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34631c54d3
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Get's the fpga building again after the git history rewrite.
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2023-12-14 17:08:25 -06:00 |
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Jacob Pease
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7e494f2d3b
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Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.
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2023-12-01 18:59:18 -06:00 |
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Jacob Pease
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71066cae12
|
Modified FPGA Makefile to override with relative path. FPGA boots now.
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2023-11-30 17:51:15 -06:00 |
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Rose Thompson
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b137759b45
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-11-20 10:34:36 -06:00 |
|
Rose Thompson
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cdd21d6635
|
Added menvcfg to debugger for checking what linux has configured.
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2023-11-19 13:44:22 -06:00 |
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Jacob Pease
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87e6a5ccf2
|
Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.
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2023-11-18 19:15:39 -06:00 |
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Jacob Pease
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ff73f798ed
|
Replaced vivado-risc-v addins directory with new SDC repo.
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2023-11-16 13:59:12 -06:00 |
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