naichewa
d67badfc60
fix hardware interlock, hold mode deassert
2023-11-08 15:20:51 -08:00
naichewa
a5837eb62c
fifo fixes and edge case testing
2023-11-07 17:59:46 -08:00
naichewa
4651b807ed
added test cases
2023-11-02 15:43:08 -07:00
naichewa
9aa8a7af3e
comments, more test cases
2023-11-01 01:26:34 -07:00
naichewa
7dd3f24d6c
Merge branch 'main' into spi
2023-10-30 17:01:41 -07:00
naichewa
2330f4ee63
hardware interlock
2023-10-30 17:00:20 -07:00
David Harris
f6a7f707bd
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
2023-10-30 09:56:17 -07:00
Rose Thompson
0fd5b3b2ce
Updated comments in the cboz tests.
2023-10-20 15:15:47 -05:00
Rose Thompson
5a4028064a
Updated comments for the cbom tests.
2023-10-20 15:13:52 -05:00
naichewa
0ff9ce527d
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
David Harris
ac4216b43d
Incorporated new AMO tests from riscv-arch-test
2023-10-16 10:25:45 -07:00
David Harris
6245748ed7
Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
2023-10-15 15:31:03 -07:00
David Harris
b4891d88db
Added WALLY minfo test for rv32
2023-10-15 06:48:22 -07:00
David Harris
434d6b2c5c
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
naichewa
aa5abfc8e8
always working after reg bit swizzle changes
2023-10-13 14:22:32 -07:00
naichewa
f231c3d3a3
correct delay0, fmt register test entries
2023-10-12 15:13:23 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
Ross Thompson
9ff3642c6c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-09-05 11:12:00 -05:00
David Harris
9747d122d2
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
David Harris
e75ceb044f
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
David Harris
1642ad2bad
Improved NAPOT test coverage
2023-08-30 21:04:36 -07:00
Ross Thompson
12c3c98824
Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.
2023-08-30 11:29:44 -05:00
David Harris
91429f3f02
Initial TLB NAPOT tests
2023-08-29 12:39:24 -07:00
David Harris
8d3ff59673
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
David Harris
0e16203cd8
Merge pull request #393 from ross144/main
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Implemented and tested CBOZ instruction
2023-08-24 19:17:38 -07:00
David Harris
c45fbe1ffe
Merge pull request #394 from harshinisrinath1001/main
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Improved testing of csri with priv.S!
2023-08-24 19:16:50 -07:00
harshinisrinath
c9112ff18d
Improved testing of csri with priv.S
2023-08-24 18:39:15 -07:00
Ross Thompson
cd3349bd26
Added rv32 cboz test.
2023-08-24 17:02:53 -05:00
Ross Thompson
914b6f9734
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
Ross Thompson
7d51690b7c
Oups forgot to include the 32-bit cbom test in previous commit.
2023-08-24 09:04:41 -05:00
David Harris
d801916d97
Merge pull request #383 from ross144/main
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Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile
2023-08-21 13:32:00 -07:00
David Harris
409abbf443
Merge pull request #381 from harshinisrinath1001/main
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Tried to improve coverage of CSRI with priv.S
2023-08-21 13:28:39 -07:00
Ross Thompson
310b700550
Have a working 32 bit cbom test!
2023-08-21 13:46:09 -05:00
Ross Thompson
d4c6ba627d
Working CBO tests for 64 bit!
2023-08-21 12:55:07 -05:00
Ross Thompson
5ed096e4bc
Made a bunch of progress towards getting cbo instructions tested.
2023-08-21 11:46:21 -05:00
harshinisrinath
3d3d15077b
cleared stimer interrupt
2023-08-20 15:42:27 -07:00
harshinisrinath
fdb7abec06
tried to improve testing of csri in privileged module
2023-08-20 15:40:02 -07:00
David Harris
2738423441
Improved CSRU coverage with priv.S
2023-08-20 12:49:31 -07:00
harshinisrinath
7494ce06eb
wrote testcase to write into FSCR
2023-08-20 12:10:08 -07:00
Ross Thompson
05d590b0b9
Fixed issue when with flush miss.
2023-08-18 16:36:13 -05:00
Ross Thompson
fc3fccafe9
Now we have invalidate, clean, and flush working.
2023-08-18 16:32:22 -05:00
Ross Thompson
4eeba9bed9
Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
2023-08-18 15:59:39 -05:00
harshinisrinath
b4cfdf3393
Fixed bug and tried to reset menvcfg to improve testing of csri in priv.
2023-07-30 16:40:06 -07:00
harshinisrinath
413a104b6c
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-07-23 11:59:43 -07:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Jacob Pease
b3aaa87cba
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
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Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
harshinisrinath
8adfcebb4f
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-07-13 13:00:58 -07:00
Kevin Kim
f6a3474550
fixed bug in testvector extract script
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-old script skips first 2 lines in rv32m case, new script only skips first line
- prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer
- prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file)
2023-06-22 09:13:22 -07:00
