Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
3,104 Commits 5 Branches 2 Tags 53 MiB
ba7f976f92
Commit Graph

3104 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Ross Thompson
d8e71e8e35 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
67ef46ea92 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
David Harris
bc2b757952 bit write update 2022-03-09 19:09:20 +00:00
David Harris
27f09ffb33 Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
David Harris
89e0830883 Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
Ross Thompson
95bb4cc8a8 Minor cleanup to interlockfsm. 2022-03-08 23:38:58 -06:00
Ross Thompson
9b113149b6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-08 18:05:35 -06:00
Ross Thompson
0310fe858f Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
75e93baaee Marked signals for name changes. 2022-03-08 17:41:02 -06:00
David Harris
00908132e6 Added more test cases and rounding modes to fma test generator 2022-03-08 23:29:29 +00:00
David Harris
8fa6a85af2 fixed setup.sh merge conflict 2022-03-08 23:21:06 +00:00
David Harris
c8f2dce026 fma16_testgen.c test cases 2022-03-08 23:18:18 +00:00
Ross Thompson
3ec32d7ce8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
d78ba777a4 Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
Ross Thompson
7b96b3f73c Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
bbracker
099fc34c10 change genTrace to dump UART output to file so we can see how far parsing got 2022-03-08 09:52:17 -08:00
bbracker
742e8d98cd fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
bfaf496473 change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers 2022-03-07 22:12:08 -08:00
bbracker
92e1583db5 change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
bbracker
097301635a change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state 2022-03-07 17:59:49 -08:00
bbracker
409dd48706 modify debug.sh to not rely on external GDB script 2022-03-07 11:56:04 -08:00
bbracker
4bf95714eb add debug.sh 2022-03-07 19:52:19 +00:00
Shreya Sanghai
c15517d334 removed reminant changes 2022-03-07 17:36:05 +00:00
Shreya Sanghai
a218a3d9fa undid changes to synth script 2022-03-07 17:32:08 +00:00
Shreya Sanghai
94a57fb6eb modified synth script to take config from outputdir 2022-03-07 17:12:43 +00:00
Shreya Sanghai
bc049e8042 updated makefile to speed up synth 2022-03-07 00:09:18 +00:00
Shreya Sanghai
a68c1c8cb1 modified makefile 2022-03-07 00:09:18 +00:00
bbracker
483aad2a05 update checkpointSweep in accordance to having removed trace parsing feature 2022-03-06 14:55:51 -08:00
bbracker
bea2faeda6 remove vestigial silencePipe mechanism 2022-03-06 14:54:35 -08:00
bbracker
11e9bbf3e4 needed to initialize checkpoint directory 2022-03-06 14:51:25 -08:00
bbracker
d007208aa9 no longer use cythonization on python parser scripts because its a little complicated and has marginal benefit 2022-03-06 14:40:26 -08:00
bbracker
f64b7776ed give genCheckpoint the same de-sudo'ing treatement 2022-03-06 14:37:12 -08:00
bbracker
7182ec228f better to use $tvDir variable rather than abs path 2022-03-06 14:33:53 -08:00
bbracker
8f2e67984f replace sudo's with suggestions in genRecording.sh 2022-03-06 14:31:55 -08:00
bbracker
e57b5208dc replace sudo's in genTrace.sh with suggested commands 2022-03-06 14:24:50 -08:00
bbracker
91f327e109 small bugfix to suggested sudo commands for linux testvectors 2022-03-06 14:16:23 -08:00
bbracker
742b9d884d remove checkpoint trace generation since that requires qemu hacking and because we are able to generate the whole trace on VLSI 2022-03-06 14:04:30 -08:00
bbracker
bb90644fb2 add path to Modelsim on vlsi 2022-03-06 13:55:19 -08:00
bbracker
e3f735cc1a recommend sudo commands without automatically executing them in genInitMem.sh 2022-03-06 13:30:19 -08:00
bbracker
efee8d3a22 change from clang to gcc when compiling testvector-generation executables 2022-03-06 13:18:53 -08:00
bbracker
b1120069a0 generate $WALLY in a way that works for bash and zsh 2022-03-06 13:12:20 -08:00
bbracker
70ddc98d19 Revert "fix "dirname: missing operand" bug from setup.sh" 
This reverts commit 60cbd1c9c1.
 2022-03-06 12:48:53 -08:00
David Harris
64d4cad288 Restored setup.sh to use . Working for David. Not sure what is happening for Ben - are you on Bash? 2022-03-06 13:39:53 +00:00
David Harris
db3b253ac1 Fixed merge of fpcalc 2022-03-06 13:32:13 +00:00
David Harris
7391c6d338 Checked in fma16_template.v 2022-03-06 13:29:35 +00:00
bbracker
1fc7856c36 add extractFunctionRadix step to buildroot Makefile 2022-03-05 19:02:07 -08:00
bbracker
4eb46785fc change genInitMem.sh to check for sufficient directory privileges rather than invoke sudo 2022-03-05 18:04:00 -08:00
bbracker
891ec82d81 remove linux-testgen dir because it is now completely obsolete 2022-03-05 17:26:30 -08:00
bbracker
60cbd1c9c1 fix "dirname: missing operand" bug from setup.sh 2022-03-05 17:21:34 -08:00