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Author SHA1 Message Date
Ross Thompson
b9a19304db Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
Ross Thompson
2e8afd071e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 13:39:47 -05:00
bbracker
5de92af0b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 05:35:56 -07:00
bbracker
735c75af55 change interrupt spoofing to happen at negative clock edges 2022-04-13 04:31:23 -07:00
bbracker
52ed99ca1b improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS 2022-04-13 03:37:53 -07:00
bbracker
6c56f52e7c fix bugs in PLIC checkpoint state parsing 2022-04-13 01:59:21 -07:00
bbracker
777de6e05b whoops fix address for PLIC int enables in checkpoint generation 2022-04-13 01:36:09 -07:00
bbracker
03f1c01f14 whoops forgot to update AttemptedInstructionCount in interrupt spoofing 2022-04-13 00:49:37 -07:00
bbracker
d3e9703c19 change testbench-linux to by default use attempted instruction count for warning/error messages 2022-04-12 21:22:08 -07:00
Ross Thompson
bb6f1cf816 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 19:38:04 -05:00
Ross Thompson
fc173a7954 Missed the force on uart for no tracking. 2022-04-12 19:37:44 -05:00
Ross Thompson
ff826fdb02 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 17:56:48 -05:00
Ross Thompson
7d0462dc59 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
ab9738d3be Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
02d6829f8e Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
f995ec2a54 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-10 13:41:27 -05:00
Ross Thompson
c3d9eafe60 Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. 2022-04-10 13:27:54 -05:00
bbracker
aa71fe542d upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs 2022-04-08 13:45:27 -07:00
bbracker
3b6cb5f0ba small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
bbracker
9cee21ea35 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-07 19:43:27 -07:00
bbracker
3c1deb551d deprecate remove_dup.awk in favor of expanding parseGDBtoTrace.py to internally remove duplicates; this way the instruction counts in traps.txt are hopefully now in sync with the line numbers of all.txt 2022-04-07 19:43:22 -07:00
Ross Thompson
43a294dc88 Added signals to ila. 2022-04-07 21:09:50 -05:00
Ross Thompson
8315d1816f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-07 16:56:56 -05:00
Ross Thompson
2294cbc1c6 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Ross Thompson
8c2382be45 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-07 16:29:48 -05:00
Ross Thompson
9db8471bf2 Added sp to ila. 2022-04-07 16:29:41 -05:00
Ross Thompson
5e4682fb65 Fixed typo in tests.vh 2022-04-07 16:28:28 -05:00
Katherine Parry
77d976a065 re-adding an empty 'vectors' folder 2022-04-07 17:44:08 +00:00
Katherine Parry
c3ac399339 cleaned floating point 'vectors' folder 2022-04-07 17:31:08 +00:00
Katherine Parry
c307cff503 fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
bbracker
1e5e2704f7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-07 08:37:44 -07:00
bbracker
95438fca0d fix parseQEMUtoGDB.py to pass on interrupt messages correctly 2022-04-07 04:47:15 -07:00
kaveh Pezeshki
7b85b39c48 using -S for busybox objdump to provide source code snippets 2022-04-06 23:06:49 +00:00
bbracker
241ec053e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-06 07:50:57 -07:00
bbracker
c9c75d2e3e filter traps list down to just interrupts 2022-04-06 07:49:44 -07:00
bbracker
241100c6ac change RAM size in genInitMem.sh 2022-04-06 07:49:04 -07:00
Kip Macsai-Goren
7425c49f58 updated test signature locations 2022-04-06 07:28:38 +00:00
Kip Macsai-Goren
618e677406 Updated trap handler to check interrupt vectoring before handling them and to use the mscratch instead of sp for a stack. 2022-04-06 07:13:51 +00:00
Kip Macsai-Goren
4a2aacadaa Updated PMA tests to comply with all width writes and reads to CLINT 2022-04-06 07:13:51 +00:00
Kip Macsai-Goren
c82667653c Added missing ZFH macro to new configs 2022-04-06 07:13:51 +00:00
David Harris
c4f5b3fd7c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-05 23:23:47 +00:00
David Harris
c22d6f2848 Added bootmem source ccode 2022-04-05 23:22:53 +00:00
Ross Thompson
9517fe9faf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-05 15:42:07 -05:00
Ross Thompson
7abde2b566 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
David Harris
ff0bddb7df Removed outdated sample testfloat calls 2022-04-04 17:23:39 +00:00
Katherine Parry
20885f4dea generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
0ed34b8e63 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
64846c800e Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
0806d1a134 Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Ross Thompson
d83db2cde5 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00