David Harris
b836679ae1
Started MMU
2021-06-04 11:59:14 -04:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
44d28dbd1c
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
bbracker
5687ab1c96
do script refactor
2021-04-24 09:32:09 -04:00
Noah Boorstin
c7a09d2359
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Noah Boorstin
5902637632
buildroot: sim is now running!
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yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9
start to add buildroot testbench
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This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
Domenico Ottolia
a149f2f3d8
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
bbracker
ce7b2314ef
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Ross Thompson
e6aef66853
Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
2021-03-23 13:54:59 -05:00
Noah Boorstin
4be19421c4
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
bbracker
eea7e2e47e
first pass at PLIC interface
2021-03-22 10:14:21 -04:00
Shreya Sanghai
dfc86539cc
Merge branch 'gshare' into main
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Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524
Switched to gshare from global history.
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Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
Noah Boorstin
847bf0b9a6
change ifndef to generate/if
2021-03-18 12:50:19 -04:00
Noah Boorstin
a226e24ed3
busybear: update memory map, add GPIO
2021-03-18 12:17:35 -04:00
Noah Boorstin
162955de69
busybear: add COUNTERS define
2021-03-16 21:08:47 -04:00
Shreya Sanghai
d9b1e7d67f
added gshare and global history predictor
2021-03-16 17:03:01 -04:00
Shreya Sanghai
a79e26f9d8
added global history branch predictor
2021-03-16 16:06:40 -04:00
Ross Thompson
8e51935082
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Noah Boorstin
0af002eb2f
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Noah Boorstin
f11b3108d8
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
Noah Boorstin
2769b147cb
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489
busybear: remove gpio, start adding 2nd ram
2021-02-28 06:02:40 +00:00
Noah Boorstin
cca60ed06d
update busybear testbench to conform to new structure
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aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
Noah Boorstin
7183910c84
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
Noah Boorstin
0fa7cffb11
busybear: lie about MISA to match OVP's MISA
2021-01-29 00:58:56 -05:00
Noah Boorstin
91dcffa26f
Update busybear tests to conform to new directory structure
2021-01-25 20:37:18 -05:00
David Harris
bf07ec92b5
Added test configurations
2021-01-25 11:28:43 -05:00
