Ross Thompson
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b5a85b55f1
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
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2022-12-23 15:10:37 -06:00 |
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Ross Thompson
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c9c83ca5ae
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Removed XEnE, YEnE, and ZEnE from forward logic.
Cleanup comments.
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2022-12-23 14:27:03 -06:00 |
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Ross Thompson
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deee433d07
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Cleanup floating point hazard logic.
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2022-12-23 14:21:47 -06:00 |
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Ross Thompson
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c8a0e7685a
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DON'T USE. First commit in attempt to move fpustall detection into the decode stage.
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2022-12-23 12:47:18 -06:00 |
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Ross Thompson
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b1aa370ff1
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Removed ZForwardEnE and replaced with ZEnE.
Similar for YForwardEnE.
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2022-12-23 12:27:51 -06:00 |
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Ross Thompson
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30dd86d146
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Removed unnecessary stall when MatchDE was driven 1 by RdE == 0.
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2022-12-23 11:45:42 -06:00 |
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David Harris
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98ecd9c77d
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Commented out fdiv early termination - broke fsqrt test
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2022-12-23 00:58:55 -08:00 |
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David Harris
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04dd3e5144
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Fixed early termination on fdivsqrt
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2022-12-23 00:53:55 -08:00 |
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David Harris
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1f6dc62bb3
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Moved InstrValidNotFLushed to csr including InstrValidM
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2022-12-23 00:27:44 -08:00 |
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David Harris
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85d0b697bf
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Removed unused StallW from CSRs
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2022-12-23 00:21:36 -08:00 |
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David Harris
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fe5b9081d9
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Removed unused signals from FPU
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2022-12-23 00:18:39 -08:00 |
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David Harris
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93bb8036be
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Revert to 98b824
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2022-12-22 23:58:14 -08:00 |
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David Harris
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a185f563f2
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Clean up unused FPU signals
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2022-12-22 23:53:09 -08:00 |
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David Harris
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74979cdc82
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FDIV merge
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2022-12-22 23:03:03 -08:00 |
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David Harris
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51b92285d3
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Removed unused signals in FPU and CSR
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2022-12-22 22:59:05 -08:00 |
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Ross Thompson
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b6b30533e8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-22 22:51:33 -06:00 |
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Ross Thompson
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6b105bd217
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Renamed IFU and LSU stalls.
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2022-12-22 21:56:33 -06:00 |
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Ross Thompson
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5a9e94048a
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The LSU is properly using FlushW rather than TrapM.
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2022-12-22 21:47:34 -06:00 |
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Ross Thompson
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ce7e1073fa
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Success we've replaced TrapM with FlushD in the IFU.
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2022-12-22 21:36:49 -06:00 |
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Ross Thompson
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677f6f8737
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Partial cleanup for BP.
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2022-12-22 20:33:38 -06:00 |
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Ross Thompson
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942acb354e
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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Ross Thompson
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7a0b3d4fc6
|
Wavefile updates.
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2022-12-22 19:45:02 -06:00 |
|
Kip Macsai-Goren
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964084f0b3
|
added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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d25d699800
|
Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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a37bde7452
|
updated trap handler alignemnts to 64 bytes in priv tests
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2022-12-22 14:23:04 -08:00 |
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Ross Thompson
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47d61984ad
|
First pass at resolving ifu flush on trap rather than FlushD.
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2022-12-22 15:53:06 -06:00 |
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David Harris
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567f76c2a5
|
Code cleanup
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2022-12-22 10:04:50 -08:00 |
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cturek
|
04bc787647
|
Added negative-result int diviison support in U and UM registers. 13 tests pass!
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2022-12-22 16:25:37 +00:00 |
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cturek
|
1712e69c73
|
Moved swap from qslc to otfc
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2022-12-22 15:44:50 +00:00 |
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cturek
|
fa03275cca
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-22 05:45:00 +00:00 |
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cturek
|
c7d0c8823f
|
Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.
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2022-12-22 05:44:55 +00:00 |
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David Harris
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4f7d9eee95
|
XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 20:39:38 -08:00 |
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Ross Thompson
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b3ff4fe02e
|
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
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2022-12-21 22:13:05 -06:00 |
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cturek
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c405dcf0cb
|
worked out some bugs with int div cycles
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2022-12-22 02:22:01 +00:00 |
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cturek
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e441f90b32
|
Renamed signals to E and M stages, forwarded preprocessed n to fsm
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2022-12-22 00:43:27 +00:00 |
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Ross Thompson
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d1aa5ba890
|
Updated cache fsm names to match book.
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2022-12-21 16:49:53 -06:00 |
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Ross Thompson
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de161c675c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-21 16:13:09 -06:00 |
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Ross Thompson
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0cb2cf9a5b
|
Changed GatedStallF to GatedStallD.
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2022-12-21 16:12:55 -06:00 |
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David Harris
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16c8655161
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 14:12:25 -08:00 |
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David Harris
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a5dc09c97f
|
Added assertion about atomics needing caches
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2022-12-21 13:57:28 -08:00 |
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Ross Thompson
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14444511a5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-21 14:57:19 -06:00 |
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Ross Thompson
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15042fc856
|
Updated fpga constraints.
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2022-12-21 14:50:01 -06:00 |
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cturek
|
2c58fd42db
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-21 20:41:38 +00:00 |
|
David Harris
|
3562542728
|
comment cleanup
|
2022-12-21 12:39:09 -08:00 |
|
David Harris
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ca949f2110
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
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cturek
|
14d9118802
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-21 19:35:57 +00:00 |
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cturek
|
6761101645
|
fixed normshift calculations
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2022-12-21 19:35:47 +00:00 |
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David Harris
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998f446e3c
|
git push
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 11:31:27 -08:00 |
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David Harris
|
820e1ab510
|
Removed unused FPU signals
|
2022-12-21 11:31:22 -08:00 |
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Ross Thompson
|
f6393d1288
|
Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
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2022-12-21 13:16:09 -06:00 |
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