Github_Repos/cvw
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6,835 Commits 5 Branches 2 Tags 53 MiB
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748 Commits

Author SHA1 Message Date
David Harris
45667c9f4d Clean up privilege rs1 decoding and implement svinval as sfence.vma 2023-07-13 02:41:17 -07:00
Ross Thompson
58dfc15844 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
c12bc4f435 Created separate temporary testbench for xcelium. 2023-07-11 15:07:33 -05:00
Ross Thompson
05b1cce2d1 RTL changes for Xcelium. 2023-07-11 10:51:02 -05:00
Ross Thompson
e647937b27 Fixed the privilege decoder bug which prevented the fpga linux boot. 2023-07-10 17:00:06 -05:00
Ross Thompson
47ee92d6e5
Merge pull request #359 from davidharrishmc/dev 
CSR updates
 2023-07-10 13:16:57 -04:00
David Harris
c91bbc3ca8 MENVCFG only exists if U_SUPPORTED 2023-07-09 18:25:07 -07:00
Ross Thompson
4e54e5169b Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
40b2f7ff9c Updated comments. 2023-07-06 15:24:26 -05:00
Ross Thompson
dc50ddd75e Removed unused parameter. 2023-07-06 14:57:07 -05:00
Ross Thompson
0394f3232f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
74a573cedd Removed outdated commment about endianness 2023-07-06 12:41:46 -07:00
David Harris
29e62f05a4 Removed MTINST, which is not used in a system without a hypervisor 2023-07-06 12:40:53 -07:00
Ross Thompson
18278b7f4d It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga. 2023-07-06 14:07:37 -05:00
Ross Thompson
ba9d5287d9 This is at least functionally correct, but has verilator lint issues. 2023-07-06 11:53:34 -05:00
Ross Thompson
930aed0898 closer, but the wally32/64priv tests are failing. 2023-07-05 17:47:38 -05:00
Ross Thompson
c0fdd3fbca Partially solved fpga boot. 2023-07-05 17:30:55 -05:00
David Harris
19efc4eda8 Fixed comment typo 2023-07-04 11:34:58 -07:00
David Harris
4f07d89d74 fixed spacing in fdivsqrt 2023-07-04 11:27:36 -07:00
David Harris
e6ba362794 Added prefetch instructions; sent cbo instructions to LSU 2023-07-02 10:55:35 -07:00
David Harris
cc87317189 Added prefetch signals 2023-07-02 10:06:58 -07:00
David Harris
a5c6ae1f78 Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions 2023-07-02 09:35:05 -07:00
David Harris
6a88ac28e4 Fixed csr typos 2023-07-02 02:01:40 -07:00
David Harris
96477a4879 Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode 2023-07-02 02:00:27 -07:00
David Harris
e2708534cd Added environment configuration control (menvcfg/senvcfg) of cbo instructions 2023-07-02 01:52:25 -07:00
David Harris
4d1ddd0c91 Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations 2023-07-02 00:34:30 -07:00
David Harris
110dd42cfb improved decoder checking atomic and RW and MW and privileged instructions 2023-07-02 00:02:03 -07:00
David Harris
07cf1dd9da improved decoder checking atomic instructions 2023-07-01 23:10:57 -07:00
David Harris
e05288afd9 Improved instruction decoding for illegal floating-point loads/stores and fences 2023-07-01 22:48:04 -07:00
Ross Thompson
1d2eb60ffb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
David Harris
95960620a2 Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
2f35bec970 FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
Ross Thompson
6d31936e89 Added comment to uart LCR to check reset value after updating FPGA. 2023-06-15 15:39:51 -05:00
Ross Thompson
34d1d50b87 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
a55bcad5c1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
David Harris
52ab586a9d Added input gating on FPU 2023-06-15 12:38:33 -07:00
David Harris
524d8e8469 Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
c7d06382b3 Bit manipulation comment cleanup 2023-06-15 12:16:46 -07:00
Ross Thompson
44c72c20e2 Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
David Harris
33ff9766b4 Gated inputs to BMU when inactive to save power and simulation time 2023-06-15 11:56:59 -07:00
Ross Thompson
2fc8080102 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
David Harris
e0b6a2d693 Fixed UART merge conflict 2023-06-15 11:36:37 -07:00
Ross Thompson
e431f90cf3 Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
37c930bb27
Update wallypipelinedsoc.sv 
Program clean up
 2023-06-15 10:39:37 -07:00
Harshini Srinath
fd00067b7f
Update wallypipelinedcore.sv 
Program clean up
 2023-06-15 10:38:38 -07:00
Harshini Srinath
e3f8280ff9
Update cvw.sv 
Program clean up
 2023-06-15 10:29:33 -07:00
Harshini Srinath
e9cfbd95f4
Update uncore.sv 
Program clean up
 2023-06-15 10:23:47 -07:00
Harshini Srinath
5d8e120031
Update uart_apb.sv 
Program clean up
 2023-06-15 10:21:46 -07:00
Harshini Srinath
53ad51ae54
Update uartPC16550D.sv 
Program clean up
 2023-06-15 10:20:29 -07:00