Ross Thompson
b3ff4fe02e
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
2022-12-21 22:13:05 -06:00
Ross Thompson
d1aa5ba890
Updated cache fsm names to match book.
2022-12-21 16:49:53 -06:00
David Harris
c26c3b76ea
Renamed renamed sram to ram
2022-12-20 08:36:45 -08:00
Ross Thompson
c3b77926d5
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
5acdf541b9
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
c985988867
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
5f556817c7
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
493b1a4280
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
3132246a46
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
91e64a0d67
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
ab3c5a0ca7
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
Ross Thompson
4a0e4aed99
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
b69aa39f30
Reduced complexity of linebytemask.
2022-12-14 09:34:29 -06:00
Ross Thompson
6d573b32d2
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
232f866ad1
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
d3b2e331c2
Added comments about why it is not possible to use FlushWay and VictimWay directly.
2022-12-09 17:07:35 -06:00
Ross Thompson
1a24e7029f
Minor simplification of cacheway way selection muxes.
2022-12-09 16:42:05 -06:00
Ross Thompson
1a9c932157
Renamed SelBusBuffer to SelFetchBuffer.
2022-12-05 17:51:13 -06:00
Ross Thompson
92066f81b6
Removed commented code.
2022-12-05 17:21:56 -06:00
Ross Thompson
37551ecc43
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
2022-12-05 17:19:51 -06:00
Ross Thompson
dc31add951
Cache signal renames.
2022-12-04 16:09:09 -06:00
Ross Thompson
9bf0eedf73
Optimized way selection logic.
2022-12-04 12:30:56 -06:00
Ross Thompson
a130a96b45
Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
2022-12-04 01:20:51 -06:00
Ross Thompson
3dea04e644
Moved selectedway mux into cacheway. It makes way more sense there.
2022-12-04 01:15:47 -06:00
Ross Thompson
f557150cae
Rename LineByteMux to FetchbufferbyteSel.
2022-12-04 01:00:04 -06:00
Ross Thompson
3442b04f9e
Properly flush cacheLRU.
2022-12-01 17:32:58 -06:00
Ross Thompson
5025664cb0
Removed unused port on cacheway.
2022-12-01 11:47:48 -06:00
Ross Thompson
a6355b1dcb
More optimization.
2022-11-30 11:26:48 -06:00
Ross Thompson
0aa7ce0b24
Removed reset on dirty cache bits.
2022-11-30 11:04:37 -06:00
Ross Thompson
cedb234013
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
2022-11-30 11:01:25 -06:00
Ross Thompson
0454eb95ad
Preparing to merge dirty and tag srams.
2022-11-30 10:40:48 -06:00
Ross Thompson
de538d1c2f
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
Ross Thompson
453ea36512
Optimization of cacheway.
2022-11-29 18:30:47 -06:00
Ross Thompson
b5718c9baa
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
2022-11-29 14:51:09 -06:00
Ross Thompson
96cc4c7ebe
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
78acd40424
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
279f5bc615
Cleanup cacheLRU.
2022-11-22 14:59:01 -06:00
Ross Thompson
e1dbe58632
File name change for cachereplacement policy to cacheLRU
2022-11-20 22:35:02 -06:00
Ross Thompson
4e926ba4cf
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
0106777f02
Finally have the correct replacement policy implementation.
2022-11-17 17:36:37 -06:00
Ross Thompson
22ad49eef2
Progress on the cache replacement policy implementation.
2022-11-16 15:35:34 -06:00
Ross Thompson
42111db671
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
2022-11-16 12:36:58 -06:00
Ross Thompson
1f21a2bab1
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
2022-11-16 11:15:34 -06:00
Ross Thompson
b53f8eceef
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
44171c342d
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
Ross Thompson
6696624971
comment updates.
2022-10-22 16:28:44 -05:00
