Ross Thompson b3ff4fe02e CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.		2022-12-21 22:13:05 -06:00
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cache.sv	Cleanup of cache flush fsm enhancement.	2022-12-16 15:36:53 -06:00
cachefsm.sv	CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.	2022-12-21 22:13:05 -06:00
cacheLRU.sv	I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.	2022-12-18 18:30:35 -06:00
cacheway.sv	Renamed renamed sram to ram	2022-12-20 08:36:45 -08:00
subcachelineread.sv	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00