David Harris
261882bf78
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
fa0080ca70
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
Ross Thompson
0438975e27
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
Ross Thompson
e0740034f0
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
Ross Thompson
f604a0d79e
cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
2022-01-05 22:56:18 -06:00
Ross Thompson
a4afc1bc54
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
e74e8c2e86
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
da585b30f9
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
Ross Thompson
7086a0ed08
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 14:15:27 -06:00
Ross Thompson
cc51a27a34
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
David Harris
6d4714651c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
da5ead23bf
Removed more generate statements
2022-01-05 16:01:03 +00:00
Ross Thompson
98be8201b2
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
fffaf654e6
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
13dbf3cc0f
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
888a60d8d6
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
Ross Thompson
cb301a78ad
Fixed bug where last line of dcache was not written back to memory on dcache flush.
2022-01-04 21:55:48 -06:00
Ross Thompson
ecc7bf5237
Fixed dcache flush.
2022-01-04 18:40:58 -06:00
David Harris
d1a7416028
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
