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Author SHA1 Message Date
David Harris
9b7f385c50 Temporary fix of InstrM to prevent testbench hanging 2023-11-03 04:59:44 -07:00
David Harris
409ecc53bd Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00
naichewa
6a148349de added test cases 2023-11-02 15:43:08 -07:00
naichewa
08cf75783e added test cases 2023-11-02 15:42:28 -07:00
Rose Thompson
3e5aa77b5d Merge branch 'main' into Zicclsm 2023-11-02 12:55:51 -05:00
Rose Thompson
7dafff27a5 Enabled Zicclsm in rv64gc. 2023-11-02 12:47:40 -05:00
Rose Thompson
92d4d7626c
Merge pull request #449 from davidharrishmc/dev 
Synthesis cleanup
 2023-11-02 12:26:55 -05:00
Rose Thompson
f89673d7e5 Doesn't yet fully work. 
Thomas is going to finish debugging while I'm on the RISCV summit next week.
 2023-11-02 12:07:42 -05:00
David Harris
c99d29cf95 Removed .gitattributes 2023-11-01 17:50:44 -07:00
Rose Thompson
3817d792f6 Progress. I think the remaining bugs are in the regression test's signature. 2023-11-01 17:51:48 -05:00
Rose Thompson
7b22b269f1 Finally the d$ spill works. At least until the next bug. Definitely needs a lot of cleanup. 2023-11-01 14:25:18 -05:00
naichewa
b59abc2dcc correct exclusion tags and reset testbench 2023-11-01 10:34:39 -07:00
naichewa
8027a71e86 harris code review 3 2023-11-01 10:14:15 -07:00
David Harris
c639f92d27 Improved comments about memory read paths 2023-11-01 07:00:17 -07:00
naichewa
755c055f74 comments, more test cases 2023-11-01 01:26:34 -07:00
Rose Thompson
b5ecae2056 Working through issues with the psill logic. 2023-10-31 18:50:13 -05:00
Rose Thompson
53bcb45844 Progress 2023-10-31 14:50:33 -05:00
naichewa
792ddec064 code review harris 2023-10-31 12:27:41 -07:00
Rose Thompson
0dd516e90f Fixed bugs in misaligned test. 2023-10-31 12:49:35 -05:00
Rose Thompson
6223e8382d First stab at the misaligned test. 2023-10-31 12:30:10 -05:00
David Harris
6f021aac54 Fixes to config extraction 2023-10-31 06:27:55 -07:00
David Harris
bd6e189680 130 nm synthesis script improvements 2023-10-30 20:57:35 -07:00
David Harris
d2ccba9a49 Conditionally instantiate hardware in ifu 2023-10-30 20:55:00 -07:00
David Harris
d0735887de Gated InstrOrigM and PCMReg when not needed 2023-10-30 20:05:37 -07:00
David Harris
4bd830e578 rom1p1r code cleanup 2023-10-30 19:47:49 -07:00
David Harris
7b3dcdc262 rom1p1r code cleanup 2023-10-30 19:46:38 -07:00
David Harris
c472f4dc3c Made 2-bit AdrReg conditional on being needed 2023-10-30 19:13:43 -07:00
naichewa
3570468ef5 Merge branch 'main' into spi 2023-10-30 17:01:41 -07:00
naichewa
7a0fb9a193 hardware interlock 2023-10-30 17:00:20 -07:00
Rose Thompson
7e8d132ead Updated mmu to not generate trap on cacheable misaligned access when supported. 
Updated tests with David's help.
 2023-10-30 18:26:11 -05:00
Rose Thompson
2f5deff7bc Preemptively fixed the bytemask bug before testing. 2023-10-30 15:47:46 -05:00
Rose Thompson
3824c3be8d rv32gc now also works with the alignment module. Still not tested with misligned access. 2023-10-30 15:30:09 -05:00
Rose Thompson
f7b00c7af9 Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests. 2023-10-30 14:54:58 -05:00
Rose Thompson
560a843cea Finally lints cleanly. 2023-10-30 14:00:49 -05:00
Rose Thompson
e3f769a563
Merge pull request #445 from davidharrishmc/dev 
Fix issue 444; no delegating misaligned instructions if they can't happen
 2023-10-30 12:25:42 -05:00
David Harris
4d191e63cc Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
David Harris
12d1aed8a9 Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported. 2023-10-30 07:06:34 -07:00
Rose Thompson
610969726e Progress. 2023-10-27 16:31:22 -05:00
Rose Thompson
b2c61737bf Passes lint with some exceptions. Still need to add misaligned store support. 2023-10-27 14:41:42 -05:00
Rose Thompson
42b2dad6ad At least have the aligner integrated, but not tested. 2023-10-27 13:55:16 -05:00
Rose Thompson
ff85832454 Addec ZICCLSM to config files and started on lsu instance. 2023-10-27 13:07:23 -05:00
Rose Thompson
d648e199e1 The misaligned load alignment lints. 2023-10-27 11:41:49 -05:00
Rose Thompson
839ff28d32 Added file. 2023-10-27 09:49:44 -05:00
Rose Thompson
e7edd0084e Progress on misaligned load/stores. 2023-10-27 09:35:44 -05:00
Rose Thompson
77e6ac487a
Merge pull request #443 from davidharrishmc/dev 
Wrapper synthesis fix.
 2023-10-27 09:25:06 -05:00
David Harris
5ca5443835 Fixed reporting of timing on modules with wrappers 2023-10-26 20:14:14 -07:00
David Harris
d5d196b870 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-26 19:02:05 -07:00
David Harris
b1796daca7
Merge pull request #441 from ross144/main 
Fixed issues #200
 2023-10-26 10:26:58 -07:00
Rose Thompson
9ca3bfc2c8 Updated comments about Interrupt and wfi. 2023-10-26 12:24:36 -05:00
Rose Thompson
63bcc7655c Forgot to include this file in the last commit. 2023-10-26 12:20:42 -05:00