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This commit is contained in:
Rose Thompson 2023-10-27 16:31:22 -05:00
parent b2c61737bf
commit 610969726e
2 changed files with 11 additions and 5 deletions
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14
src/cache/cache.sv vendored
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@ -175,10 +175,16 @@ module cache import cvw::*; #(parameter cvw_t P,
logic [LINELEN/8-1:0] DemuxedByteMask, FetchBufferByteSel;
// Adjust byte mask from word to cache line
onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
for(index = 0; index < 2**LOGCWPL; index++) begin
assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
end
localparam CACHEMUXINVERALPERLINE = LINELEN/MUXINTERVAL;// Number of words in cache line
localparam LOGMIPL = $clog2(CACHEMUXINVERALPERLINE);// Log2 of ^
logic [LINELEN/8-1:0] BlankByteMask;
assign BlankByteMask[WORDLEN/8-1:0] = ByteMask;
assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = '0;
assign DemuxedByteMask = BlankByteMask << ((MUXINTERVAL/8) * WordOffsetAddr);
assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1.
// Merge write data into fetched cache line for store miss

2
src/lsu/align.sv
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@ -64,7 +64,7 @@ module align import cvw::*; #(parameter cvw_t P) (
////////////////////////////////////////////////////////////////////////////////////////////////////
localparam LLENINBYTES = P.LLEN/8;
logic [XLEN-1:0] IEUAdrIncrementM;
logic [P.XLEN-1:0] IEUAdrIncrementM;
assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
mux2 #(P.XLEN) ieuadrspillemux(.d0(IEUAdrE), .d1(IEUAdrIncrementM), .s(SelSpillE), .y(IEUAdrSpillE));
mux2 #(P.XLEN) ieuadrspillmmux(.d0({IEUAdrM[P.XLEN-1:2], 2'b10}), .d1(IEUAdrIncrementM), .s(SelSpillM), .y(IEUAdrSpillM));