David Harris
21acb5e4e8
mmu cleanup
2023-01-14 18:27:53 -08:00
David Harris
894fdb8863
mmu cleanup
2023-01-14 18:20:47 -08:00
David Harris
316690c929
mmu cleanup
2023-01-14 18:14:38 -08:00
David Harris
00500c6685
mmu cleanup
2023-01-14 17:49:10 -08:00
David Harris
bba08c3202
mmu cleanup
2023-01-14 17:35:21 -08:00
David Harris
7d93659f6b
changed name to CORE-V-WALLY
2023-01-11 15:15:08 -08:00
David Harris
b911056e66
Changed Wally to CORE-V Wally
2023-01-11 14:03:44 -08:00
David Harris
e92cffbb5e
Changed MIT license to Solderpad License
2023-01-10 11:35:20 -08:00
David Harris
9bdf79bfe6
Removed unused signals; added check for atomic in pmachecker
2023-01-07 05:59:56 -08:00
David Harris
6763f51b3c
code cleanup
2023-01-07 04:49:25 -08:00
Ross Thompson
b5a85b55f1
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
a58fbd618e
Moved CPUBusy out of HPTW.
2022-12-11 15:48:00 -06:00
Ross Thompson
fbf543bf57
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
3df51716b1
Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
2022-11-14 16:02:20 -06:00
David Harris
6372139af4
Removed comment about nonexistent possible bug
2022-11-14 09:56:33 -08:00
David Harris
06dbed92c8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 09:52:24 -08:00
David Harris
f9202187ba
Removed comment about nonexistent possible bug
2022-11-14 09:52:21 -08:00
Ross Thompson
9d7ba19fe1
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
421c6f9c48
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
879e62912b
HPTW cleanup
2022-11-13 04:23:23 -08:00
Ross Thompson
c028306ba3
Fixed name change in hptw.
2022-11-10 16:13:31 -06:00
Ross Thompson
40367eaf45
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
f7b94c12fc
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
David Harris
60cfa0d69c
HPTW cleanup
2022-11-04 15:21:09 -07:00
Ross Thompson
51408c620e
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
cabcb5e89e
Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
...
Don't use this commit as the rv32i tests are not passing.
2022-10-05 14:51:02 -05:00
Ross Thompson
122c88ee46
Created two new pma regions for dtim and irom.
2022-08-28 13:50:50 -05:00
Ross Thompson
5e63af5887
Reordered the adrdecs.
2022-08-28 13:38:57 -05:00
David Harris
f2517f8290
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
David Harris
37f0b52520
Fixed address decoder hanging buildroot
2022-08-26 22:01:25 -07:00
David Harris
2b241f8bbd
Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding
2022-08-26 21:18:18 -07:00
David Harris
03e731b3ff
Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
2022-08-26 21:05:20 -07:00
David Harris
f0b4f69b65
Added IROM and DTIM decoding to adrdecs
2022-08-26 20:45:43 -07:00
Ross Thompson
769af32f2a
Renamed RAM to UNCORE_RAM.
2022-08-24 18:09:07 -05:00
Ross Thompson
20ba6fd19c
Reversed order of supported sized in adrdecs.
2022-08-23 11:14:53 -05:00
Ross Thompson
3b07584403
Updated the names of the *WriteDataM inside the LSU to more meaningful names.
...
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
2022-08-23 10:34:39 -05:00
David Harris
ea153e0aad
Removed FStore2 and simplified HPTW
2022-08-22 13:29:54 -07:00
Madeleine Masser-Frye
b5454f3a55
took first match out of pmpadrdec
2022-07-06 00:02:01 +00:00
David Harris
fb725a9e0a
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
8372bc86a7
Removing unused signals
2022-05-12 14:36:15 +00:00
David Harris
8066ba45e8
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
Ross Thompson
dc48d84dd6
Modified clint to support all byte write sizes.
2022-03-31 11:31:52 -05:00
Ross Thompson
7a824eaae1
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
David Harris
f0a7ae2bba
adrdecs comments
2022-02-28 20:33:41 +00:00
David Harris
e108eb5195
Modified address decoder for native access to CLINT
2022-02-28 19:13:14 +00:00
David Harris
3519a20ccf
hptw cleanup for synthesis
2022-02-28 05:54:34 +00:00
Ross Thompson
2f711fb642
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
0c65ea96d8
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
