slmnemo
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0bfc3fda1b
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
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Daniel Torres
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b726b05d61
|
fixed wally rv32e tests, updated regression makefile to new testflow
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2022-07-22 17:09:46 -07:00 |
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Katherine Parry
|
ee7932c804
|
divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
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Daniel Torres
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d95b266d49
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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2bbfd67082
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
44c30ec082
|
fixed error in tests.vh
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2022-07-22 14:55:55 -07:00 |
|
slmnemo
|
170601af0b
|
Added UART test to peripheral test
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2022-07-22 14:55:34 -07:00 |
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Daniel Torres
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fbe3a1af12
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 13:52:19 -07:00 |
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Daniel Torres
|
261b9aa5a1
|
commented out embench test that should be commented out
|
2022-07-22 13:52:13 -07:00 |
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slmnemo
|
49329b3f42
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 12:36:06 -07:00 |
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slmnemo
|
0d98ff74b4
|
Added PLIC test to regression
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2022-07-22 12:35:37 -07:00 |
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Daniel Torres
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5d7171f6f8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
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526f70e772
|
commiting current changes to riscof wally tests
|
2022-07-22 11:14:04 -07:00 |
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cturek
|
338f44dfc8
|
Square root negative exponent handling
|
2022-07-22 16:45:19 +00:00 |
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slmnemo
|
49565f944c
|
Added PLIC and UART tests and new functions to the test library
|
2022-07-22 07:10:39 -07:00 |
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David Harris
|
07c946bb04
|
Reset MSR on read
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2022-07-22 04:29:27 +00:00 |
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Daniel Torres
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f1578936b8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 20:59:01 -07:00 |
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Daniel Torres
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bd918d37ba
|
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
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2022-07-21 20:58:58 -07:00 |
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slmnemo
|
99dcff80c9
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-21 20:35:52 -07:00 |
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slmnemo
|
bfa500234d
|
Fixed UART bug related to parity and MSR/LSR
|
2022-07-21 20:35:46 -07:00 |
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cturek
|
c170a8d9b6
|
Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder
|
2022-07-22 01:27:08 +00:00 |
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cturek
|
abe1ff906e
|
Renamed variables, moved output handling to postprocessor, added remainder handling
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2022-07-21 20:45:08 +00:00 |
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Daniel Torres
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a17361870f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 12:50:04 -07:00 |
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Daniel Torres
|
6e9b4f4075
|
removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
|
2022-07-21 12:47:51 -07:00 |
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Katherine Parry
|
e330a840b0
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-21 19:38:15 +00:00 |
|
Katherine Parry
|
270216dd02
|
radix-4 division integrated into srt - not tested
|
2022-07-21 19:38:06 +00:00 |
|
cturek
|
ddc237f6bc
|
Division working too
|
2022-07-21 17:59:10 +00:00 |
|
cturek
|
9c694b887e
|
Updated Radix2 Sqrt to follow new algorithm
|
2022-07-21 17:36:21 +00:00 |
|
Katherine Parry
|
67c99d3d1a
|
added input enables and improved forwarding
|
2022-07-21 01:20:06 +00:00 |
|
Katherine Parry
|
e8c9830b88
|
turn off 2 word store durring non-fp instructions
|
2022-07-20 21:57:23 +00:00 |
|
Ross Thompson
|
9868e685a4
|
Minor cleanup of cache.
|
2022-07-19 23:04:23 -05:00 |
|
Ross Thompson
|
6c8ac7851e
|
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
|
2022-07-19 22:42:25 -05:00 |
|
Katherine Parry
|
fb890d621d
|
moved ctrl signal registers into fctrl, also a lot of code cleaning
|
2022-07-20 02:27:39 +00:00 |
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cturek
|
d7e90a7086
|
divsqrt working for floating point
|
2022-07-20 02:04:20 +00:00 |
|
cturek
|
8e66b81821
|
New radix-2 algorithm implemented and working
|
2022-07-20 02:00:43 +00:00 |
|
cturek
|
db39a05abc
|
small changes
|
2022-07-20 01:36:25 +00:00 |
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Katherine Parry
|
531829f7c8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-19 23:44:41 +00:00 |
|
Katherine Parry
|
afcddf7035
|
oprimized zeros and replaced complex ?: with always_comb
|
2022-07-19 23:44:37 +00:00 |
|
Daniel Torres
|
d33d0d22bd
|
commented out embench 2.0 tests
|
2022-07-19 13:36:18 -07:00 |
|
Ross Thompson
|
ffda64587c
|
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
|
2022-07-18 23:37:18 -05:00 |
|
Katherine Parry
|
4c2afbbc4f
|
moved Se into execute stage
|
2022-07-19 01:10:10 +00:00 |
|
Katherine Parry
|
a590728350
|
reworked fmashiftcalc to match book
|
2022-07-19 00:04:24 +00:00 |
|
David Harris
|
59eb11b73a
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-18 23:11:12 +00:00 |
|
Katherine Parry
|
e599f82b29
|
moved Ss to execute stage
|
2022-07-18 20:48:56 +00:00 |
|
Katherine Parry
|
921debf930
|
removed underflow from inexactct calculation
|
2022-07-18 17:51:18 +00:00 |
|
Katherine Parry
|
ea7b32a50b
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-18 17:31:29 +00:00 |
|
Katherine Parry
|
5bb1478859
|
renamed signals in ocde to match book
|
2022-07-18 17:31:17 +00:00 |
|
Ross Thompson
|
a88543275f
|
Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
|
2022-07-17 21:05:31 -05:00 |
|
Ross Thompson
|
3670c47141
|
Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
|
2022-07-17 16:20:04 -05:00 |
|
David Harris
|
7c744f0053
|
Rewrote convert shift calculation with always for ease of reading
|
2022-07-17 16:40:58 +00:00 |
|
David Harris
|
6e1d4ec4ed
|
restored intPending logic to be sticky for PLIC
|
2022-07-16 17:43:31 -07:00 |
|
Katherine Parry
|
a4cd157f00
|
forgot some files
|
2022-07-15 21:42:45 +00:00 |
|
Katherine Parry
|
e498d87c5c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-15 20:17:08 +00:00 |
|
Katherine Parry
|
e251022269
|
merged floating-point radix-2 divider with radix-4
|
2022-07-15 20:16:59 +00:00 |
|
cturek
|
ec9536f983
|
Square root radix 2 working, does not work with division
|
2022-07-14 22:52:09 +00:00 |
|
cturek
|
9f18f6a203
|
Square root
|
2022-07-14 21:19:45 +00:00 |
|
cturek
|
38bbd19abf
|
Six tests passing and a bunch of sizizing issues fixed
|
2022-07-14 19:38:27 +00:00 |
|
Katherine Parry
|
a0e9e93d4f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-14 18:16:13 +00:00 |
|
Katherine Parry
|
b069cfbec2
|
fixed error in divsqrt
|
2022-07-14 18:16:00 +00:00 |
|
cturek
|
f49c2a969f
|
S and SM are updating but are not correct yet
|
2022-07-14 00:39:30 +00:00 |
|
Katherine Parry
|
e5a8ac2a44
|
renamed a file to fit diagram
|
2022-07-13 23:44:54 +00:00 |
|
cturek
|
7629173b15
|
DIVLEN and counter updated for sqrt computation and rounding
|
2022-07-13 22:42:39 +00:00 |
|
Katherine Parry
|
7e163e22a3
|
some code cleanup
|
2022-07-13 15:28:22 -07:00 |
|
Katherine Parry
|
77ea4e47cb
|
removed minus 1 case in rounding
|
2022-07-13 15:01:38 -07:00 |
|
cturek
|
d57fb6f98a
|
radix 4 files removed from srt and divlen modified for sqrt
|
2022-07-13 19:46:48 +00:00 |
|
cturek
|
9b7e63f482
|
Lint error fixed and added comments to preprocessing
|
2022-07-13 19:34:04 +00:00 |
|
cturek
|
81f396f885
|
Testbench accepts standard test vector files
|
2022-07-13 18:30:18 +00:00 |
|
cturek
|
11bb3f0a3e
|
Test generation files in common format
|
2022-07-13 18:11:13 +00:00 |
|
cturek
|
110b762b55
|
Finalized sqrt, ready for debugging
|
2022-07-13 17:56:23 +00:00 |
|
cturek
|
31db938e7e
|
Added adder input selection to on the fly converter
|
2022-07-13 17:47:27 +00:00 |
|
cturek
|
bb7e73abf0
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-13 17:36:56 +00:00 |
|
Katherine Parry
|
26e39dd325
|
removed the +1 in the cvt
|
2022-07-13 09:41:35 -07:00 |
|
Katherine Parry
|
e05b2a07d2
|
removed warnings and took a mux out of the critical path
|
2022-07-12 18:32:17 -07:00 |
|
cturek
|
5c9f011561
|
little fix
|
2022-07-12 23:04:33 +00:00 |
|
cturek
|
ed9106128f
|
Square root implemented
|
2022-07-12 22:45:54 +00:00 |
|
Katherine Parry
|
452b017f9a
|
found the bug in the store modification
|
2022-07-12 22:42:19 +00:00 |
|
Katherine Parry
|
2ada8a8bc1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-12 22:37:20 +00:00 |
|
cturek
|
9d4acc9ddb
|
C register and other various fixes
|
2022-07-12 22:18:56 +00:00 |
|
cturek
|
3483b92480
|
On the fly conversion for square root
|
2022-07-12 02:21:38 +00:00 |
|
Katherine Parry
|
5c0ecfa433
|
forgot a file
|
2022-07-11 18:31:51 -07:00 |
|
Katherine Parry
|
7815b81716
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-11 18:30:29 -07:00 |
|
Katherine Parry
|
b728e5054d
|
variable interations implemented in radix-4 divider
|
2022-07-11 18:30:21 -07:00 |
|
DTowersM
|
191c7a2ee3
|
added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
|
2022-07-11 21:13:09 +00:00 |
|
David Harris
|
2bc8ff555b
|
added comment about checking SRAM size
|
2022-07-10 12:48:51 +00:00 |
|
David Harris
|
9cb675b2e4
|
added comment about RAMs in cacheway
|
2022-07-10 12:47:34 +00:00 |
|
Katherine Parry
|
ca4fe08fd9
|
renamed FLoad2 to FStore2
|
2022-07-09 00:26:45 +00:00 |
|
Katherine Parry
|
cd53ae67d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
cturek
|
2dc074ea93
|
F Selection
|
2022-07-08 21:53:52 +00:00 |
|
Katherine Parry
|
3476579e02
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-08 12:30:50 -07:00 |
|
Katherine Parry
|
9ef45f36fd
|
renamed signals in cvt and prostproc
|
2022-07-08 12:30:43 -07:00 |
|
James Stine
|
c5dfefe669
|
Update SRAM to /proj/wally
|
2022-07-08 08:09:55 -05:00 |
|
David Harris
|
d10ad0e883
|
Removed testbench code that ignores mismatch on zero signatures
|
2022-07-08 09:17:31 +00:00 |
|
David Harris
|
c72e4d43d2
|
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-08 09:09:07 +00:00 |
|
David Harris
|
381f3298d8
|
Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
|
2022-07-08 09:09:02 +00:00 |
|
David Harris
|
1ce0975366
|
Adjusting byte writes to RAM
|
2022-07-08 08:45:21 +00:00 |
|
David Harris
|
3f9e662201
|
Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
|
2022-07-08 08:44:37 +00:00 |
|
David Harris
|
9b6d9666c5
|
Removed unused swbytemask from CLINT
|
2022-07-08 08:43:24 +00:00 |
|
Katherine Parry
|
905b7ffc84
|
moved unsused division code again
|
2022-07-07 16:41:26 -07:00 |
|
cturek
|
b7e590ebb0
|
Sqrt exponents
|
2022-07-07 23:34:56 +00:00 |
|
Katherine Parry
|
5751d86f69
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-07 16:29:44 -07:00 |
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