90 Commits

Author	SHA1	Message	Date
Ross Thompson	b0f0fb1da7	Adding in the ILA to the arty a7.	2023-04-17 14:54:10 -05:00
Ross Thompson	5591b447d6	Fixed more issues with arty a7 constarints.	2023-04-16 13:25:02 -05:00
Ross Thompson	f4734c0d1b	Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. ... mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.	2023-04-15 11:13:28 -05:00
Ross Thompson	2f8359e6cc	Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.	2023-04-14 18:02:16 -05:00
Ross Thompson	4563b650bf	Fixed more bugs in the ila debug constraints.	2023-04-11 14:32:53 -05:00
Ross Thompson	e490ab09cf	Updated to help debut Jacob's crossbar woes.	2023-04-11 14:22:42 -05:00
Ross Thompson	6c07a2e595	Fixed sum bugs with arty a7 ila script.	2023-04-11 10:00:06 -05:00
Ross Thompson	c4e5b8db49	Updates for arty a7.	2023-04-10 17:02:19 -05:00
Ross Thompson	5bcb0f6ace	Fixed syntax errors in arty7 top level.	2023-04-10 16:08:40 -05:00
Ross Thompson	0700202001	Added more support for Arty A7 board.	2023-04-10 16:01:17 -05:00
Ross Thompson	e7f494ef95	Started putting together the arty a7 board package files.	2023-04-10 13:15:55 -05:00
Ross Thompson	1986ef0625	Started constrains file for arty a7 fpga.	2023-03-24 20:38:13 -05:00
Ross Thompson	576d37eb8c	Updated fpga constraints to remove critical warning.	2023-03-24 19:09:36 -05:00
Ross Thompson	be0318209e	Updated fpga ila script.	2023-03-06 13:14:48 -06:00
Ross Thompson	ff7dc4f34a	fpga constraints updates	2023-02-07 15:22:14 -06:00
Ross Thompson	2fc47bab9c	More fixes for the debug2.xdc constraints.	2023-01-20 20:48:19 -06:00
Ross Thompson	61efb22db1	More fixes to fpga ila debugger.	2023-01-20 20:28:21 -06:00
Ross Thompson	e28ea2d630	Fixed fpga constraints.	2023-01-20 20:18:04 -06:00
Ross Thompson	0ed9811e31	Updated fpga constraints.	2023-01-20 20:16:33 -06:00
Ross Thompson	25bd2e4670	Removed mark_debug vivado directive from source code. ... Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory.	2023-01-20 19:43:18 -06:00
Ross Thompson	6ccb3a0147	Test commit.	2023-01-20 17:27:09 -06:00
Ross Thompson	11c6106022	Repaired fpga debugger.	2023-01-20 15:26:52 -06:00
Ross Thompson	e0ec45489a	Updated constraints to remove DivBusyE.	2022-12-30 10:51:35 -06:00
Ross Thompson	138c3542db	Updated fpga constraints.	2022-12-24 10:21:16 -06:00
Ross Thompson	b5a85b55f1	Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. ... Generate WFIStallM in the privileged unit rather than generate in hazard. Cleaned up the hazard cause logic to be consistent across all causes.	2022-12-23 15:10:37 -06:00
Ross Thompson	6b105bd217	Renamed IFU and LSU stalls.	2022-12-22 21:56:33 -06:00
Ross Thompson	15042fc856	Updated fpga constraints.	2022-12-21 14:50:01 -06:00
Ross Thompson	13beda7d0c	Updated vcu118 piniout.	2022-12-18 14:00:10 -06:00
Ross Thompson	3ee6ed8542	Updated fpga constraints	2022-12-15 16:45:55 -06:00
rachanaerra	10ff69efc1	updated constraints file	2022-12-05 15:05:21 -06:00
Ross Thompson	30b2bd263c	Updates to fpga constraints.	2022-11-09 13:52:36 -06:00
Jacob Pease	160ca366c8	Added PLIC signals for debugging on FPGA.	2022-10-25 13:57:09 -05:00
Ross Thompson	9ba487c323	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
Ross Thompson	92ace4d8f7	Forget to include updated xdc file.	2022-10-24 13:51:21 -05:00
Ross Thompson	a008c61939	Updated debug2.xdc for interlock fsm changes.	2022-10-19 17:34:47 -05:00
Ross Thompson	2d063bbb2d	Updated constraints file to work with alternate uart.	2022-10-04 17:35:44 -05:00
Ross Thompson	16e10a4c5b	added new constraints for fpga.	2022-09-17 22:20:06 -05:00
Ross Thompson	787f5bcccb	Fixed fpga debug constraints.	2022-09-03 17:36:29 -05:00
Ross Thompson	4d60d9a840	Fixed up FPGA constraints. ... Added back in the fpga boot rom preload.	2022-09-02 13:54:35 -05:00
Ross Thompson	01a7718471	Added generate around ebu.	2022-08-25 09:24:13 -05:00
Ross Thompson	701324eeb8	Updated ila signals. ... Improve fpga wave config. added back in the fpga preload.	2022-08-25 09:03:29 -05:00
Ross Thompson	8180d1ade4	Updated fpga debugger to latest RTL version.	2022-08-19 17:13:36 -05:00
Ross Thompson	8b2491c169	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-19 16:39:28 -05:00
Ross Thompson	83bca570ae	Modified debugger for updated rtl.	2022-06-04 14:39:55 -05:00
Ross Thompson	1318f702cf	Added more debug signals to uart.	2022-05-21 19:47:40 -05:00
Ross Thompson	db85afcd2d	Added more plic debugging signals.	2022-05-21 14:04:08 -05:00
Ross Thompson	6cae5aa88f	Updated the fpga constraints.	2022-05-21 13:32:03 -05:00
Ross Thompson	9079e67aae	Updated fpga debugger.	2022-05-17 23:04:01 -05:00
Ross Thompson	51add16def	Updated debugger constraints.	2022-05-09 10:19:25 -05:00
Ross Thompson	c045e3afd8	Added back the instret counter to ILA.	2022-04-17 18:44:07 -05:00