Ross Thompson
87d3869a6e
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
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I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Ross Thompson
e09ac73eaf
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
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Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
Ross Thompson
a7e4d39ea1
Fixed issue with not saving the first cache block read on a miss spill.
2021-04-26 12:57:34 -05:00
bbracker
7947858481
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
8d77012995
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Ross Thompson
c9bdaceddb
Fixed icache for 32 bit.
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Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
7c8d2e9b78
Partially working icache.
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The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Ross Thompson
50e893eec9
Fixed for the instruction spills.
2021-04-21 16:47:05 -05:00
Teo Ene
008b308b79
Fixed most relevant remaining synthesis compilation warnings with Ben
2021-04-21 16:06:27 -05:00
Ross Thompson
269ea7997c
major progress.
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It's running the icache is imperas tests now.
Compressed does not work yet.
2021-04-21 08:39:54 -05:00
Ross Thompson
a861a37b72
Why was the linter messed up?
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There are a number of combo loops which need fixing outside the icache. They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261
Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.
2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Jarred Allen
4d58f673b2
Add a comment to explain a detail
2021-04-14 23:14:59 -04:00
Jarred Allen
c32fe09056
More icache bugfixes
2021-04-14 19:03:33 -04:00
Teo Ene
0bffac2c74
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Jarred Allen
357aed75ee
A few more cache fixes
2021-04-13 01:07:40 -04:00
Jarred Allen
4da2688c40
Fix another bug in icache
2021-04-06 17:47:00 -04:00
Jarred Allen
ecb2bc8163
Fix another bug in icache
2021-04-06 12:48:42 -04:00
Jarred Allen
4ebc991a65
Fix bug in icache
2021-04-03 18:10:54 -04:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Jarred Allen
c8a88757ab
Fix error when reading an instruction that crosses a line boundary
2021-03-25 18:47:23 -04:00
Jarred Allen
7338ddf853
Remove old icache
2021-03-25 15:46:35 -04:00
Jarred Allen
fa6e6f1724
Works for misaligned instructions not on line boundaries
2021-03-25 15:42:17 -04:00
Jarred Allen
73d4dd8c15
Begin work on compressed instructions
2021-03-25 14:43:10 -04:00
Jarred Allen
feabcf2d50
Make cache output NOP after a reset
2021-03-25 13:18:30 -04:00
Jarred Allen
e8e4e1bee2
rv64i linear control flow now working
2021-03-25 13:02:26 -04:00
Jarred Allen
08f4ce4438
More progress on icache controller
2021-03-25 13:01:11 -04:00
Jarred Allen
fff70bccbc
Begin rewrite of icache module to use a direct-mapped scheme
2021-03-25 13:01:10 -04:00
Jarred Allen
abedaf62a8
Output NOP instead of BAD when reset
2021-03-25 12:42:48 -04:00
Jarred Allen
34cc9b4aeb
Document some internal signals
2021-03-23 00:10:35 -04:00
Jarred Allen
e4ebb4e31e
Add comments explaining icache inputs
2021-03-23 00:07:39 -04:00
Jarred Allen
c47a80213e
Small commit to see if new hook tests non-main branch
2021-03-22 23:57:01 -04:00
Jarred Allen
307e33bc7e
Remove DelaySideD since it isn't needed
2021-03-22 15:13:23 -04:00
Jarred Allen
99fa8beef3
Update icache interface
2021-03-22 15:04:46 -04:00
Jarred Allen
066dc2caac
Fix bug with PC incrementing
2021-03-20 18:06:03 -04:00
Jarred Allen
665c244ba1
Fix another bug in the icache (why so many of them?)
2021-03-20 17:54:40 -04:00
Jarred Allen
43a8cb0354
Revert "Change flop to listen to StallF"
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This reverts commit f069b759be
2021-03-20 17:34:19 -04:00
Jarred Allen
f069b759be
Change flop to listen to StallF
2021-03-20 17:04:13 -04:00
Jarred Allen
3fc36b978d
Fix icache for jumping into misaligned instructions
2021-03-16 16:57:51 -04:00
Jarred Allen
5b174adc2a
Fix BEQZ tests
2021-03-14 15:42:27 -04:00
Jarred Allen
c2f2caa3f6
Get non-jump case working
2021-03-14 14:46:21 -04:00
Jarred Allen
81b29a3891
More progress
2021-03-09 21:16:07 -05:00
Jarred Allen
5da98b5381
Partial progress towards compressed instructions
2021-03-04 18:30:26 -05:00
Jarred Allen
b0f4d8e8d4
Remove rd2, working for non-compressed
2021-03-04 16:46:43 -05:00
