652 Commits

Author	SHA1	Message	Date
Katherine Parry	afcddf7035	oprimized zeros and replaced complex ?: with always_comb	2022-07-19 23:44:37 +00:00
Katherine Parry	4c2afbbc4f	moved Se into execute stage	2022-07-19 01:10:10 +00:00
Katherine Parry	a590728350	reworked fmashiftcalc to match book	2022-07-19 00:04:24 +00:00
David Harris	59eb11b73a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 23:11:12 +00:00
Katherine Parry	e599f82b29	moved Ss to execute stage	2022-07-18 20:48:56 +00:00
Katherine Parry	921debf930	removed underflow from inexactct calculation	2022-07-18 17:51:18 +00:00
Katherine Parry	ea7b32a50b	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 17:31:29 +00:00
Katherine Parry	5bb1478859	renamed signals in ocde to match book	2022-07-18 17:31:17 +00:00
David Harris	7c744f0053	Rewrote convert shift calculation with always for ease of reading	2022-07-17 16:40:58 +00:00
David Harris	6e1d4ec4ed	restored intPending logic to be sticky for PLIC	2022-07-16 17:43:31 -07:00
Katherine Parry	a4cd157f00	forgot some files	2022-07-15 21:42:45 +00:00
Katherine Parry	e251022269	merged floating-point radix-2 divider with radix-4	2022-07-15 20:16:59 +00:00
Katherine Parry	b069cfbec2	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
Katherine Parry	e5a8ac2a44	renamed a file to fit diagram	2022-07-13 23:44:54 +00:00
Katherine Parry	7e163e22a3	some code cleanup	2022-07-13 15:28:22 -07:00
Katherine Parry	77ea4e47cb	removed minus 1 case in rounding	2022-07-13 15:01:38 -07:00
Katherine Parry	26e39dd325	removed the +1 in the cvt	2022-07-13 09:41:35 -07:00
Katherine Parry	e05b2a07d2	removed warnings and took a mux out of the critical path	2022-07-12 18:32:17 -07:00
Katherine Parry	452b017f9a	found the bug in the store modification	2022-07-12 22:42:19 +00:00
Katherine Parry	2ada8a8bc1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-12 22:37:20 +00:00
Katherine Parry	5c0ecfa433	forgot a file	2022-07-11 18:31:51 -07:00
Katherine Parry	7815b81716	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-11 18:30:29 -07:00
Katherine Parry	b728e5054d	variable interations implemented in radix-4 divider	2022-07-11 18:30:21 -07:00
David Harris	2bc8ff555b	added comment about checking SRAM size	2022-07-10 12:48:51 +00:00
David Harris	9cb675b2e4	added comment about RAMs in cacheway	2022-07-10 12:47:34 +00:00
Katherine Parry	ca4fe08fd9	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
Katherine Parry	cd53ae67d9	moved fpu ieu write data mux to lsu	2022-07-08 23:56:57 +00:00
Katherine Parry	3476579e02	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-08 12:30:50 -07:00
Katherine Parry	9ef45f36fd	renamed signals in cvt and prostproc	2022-07-08 12:30:43 -07:00
James Stine	c5dfefe669	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00
David Harris	c72e4d43d2	erge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-08 09:09:07 +00:00
David Harris	381f3298d8	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
David Harris	1ce0975366	Adjusting byte writes to RAM	2022-07-08 08:45:21 +00:00
David Harris	3f9e662201	Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables	2022-07-08 08:44:37 +00:00
David Harris	9b6d9666c5	Removed unused swbytemask from CLINT	2022-07-08 08:43:24 +00:00
Katherine Parry	905b7ffc84	moved unsused division code again	2022-07-07 16:41:26 -07:00
Katherine Parry	2bbde827e6	Revert "moved old divsqrt to unusedsrc" ... This reverts commit c9f5ae12ea.	2022-07-07 16:29:17 -07:00
Katherine Parry	c9f5ae12ea	moved old divsqrt to unusedsrc	2022-07-07 16:09:56 -07:00
Katherine Parry	41c16be012	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
David Harris	96a75d7749	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-07 22:00:59 +00:00
Katherine Parry	08769e35ae	modified wally shared	2022-07-07 21:59:43 +00:00
David Harris	2f342c430e	fixing port errors	2022-07-07 21:57:10 +00:00
Katherine Parry	0b40f38f02	added load and store test	2022-07-07 21:48:51 +00:00
David Harris	88e3233935	Preliminary SRAM integration	2022-07-07 19:56:20 +00:00
David Harris	08ae2db080	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-06 23:43:05 +00:00
Ross Thompson	bd46cf76a9	Fixed an issue with direct map cache's nextway logic. ... Also found a small error in the replacement policy.	2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye	cb33d2289b	fixed width mismatch for rv64 ieuadrM and readdatawordM	2022-07-06 22:39:35 +00:00
David Harris	9ef38145d7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-06 13:26:26 +00:00
David Harris	a599084b88	PLIC and UART passing tests on APB	2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye	846f12aa2e	new priority onehot module for better area/time	2022-07-06 00:08:59 +00:00