James Stine c5dfefe669 Update SRAM to /proj/wally		2022-07-08 08:09:55 -05:00
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cache	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00
ebu	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
fpu	moved old divsqrt to unusedsrc	2022-07-07 16:09:56 -07:00
generic	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
hazard	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
ieu	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
ifu	fixed width mismatch for rv64 ieuadrM and readdatawordM	2022-07-06 22:39:35 +00:00
lsu	APB CLINT passing regression	2022-07-05 15:51:35 +00:00
mmu	took first match out of pmpadrdec	2022-07-06 00:02:01 +00:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.	2022-06-02 14:18:55 +00:00
uncore	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
wally	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00