Ross Thompson
ae0cc085b4
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
...
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
Ross Thompson
7b99df2f1c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-21 22:38:05 -06:00
Ross Thompson
42ad710213
linux-wave.do changes.
2021-12-21 22:37:55 -06:00
David Harris
8a37478332
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-22 03:59:14 +00:00
David Harris
79d2aacf80
Fixed directory in Makefile for exe2memfile
2021-12-22 03:59:08 +00:00
Ross Thompson
50e4463a7f
It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
2021-12-21 15:59:56 -06:00
Ross Thompson
4ae15bf5e4
Fixed bug where the wrong address is read into the icache memory.
2021-12-21 15:16:00 -06:00
Ross Thompson
0a7dc96052
Fixed complex bug where FENCE is instruction class miss predicted as a taken branch.
2021-12-21 11:29:28 -06:00
Ross Thompson
b0507b96b0
Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE.
2021-12-20 23:45:55 -06:00
Ross Thompson
a02ac78907
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 23:27:46 -06:00
Ross Thompson
0bc3bcf406
Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address.
2021-12-20 23:27:37 -06:00
David Harris
075a24f182
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:16:25 -08:00
David Harris
c5903b14bb
Renamed to setup.sh and fixed path bug
2021-12-20 21:14:35 -08:00
David Harris
75c5e74422
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-21 05:10:17 +00:00
David Harris
97cd6aca1e
Improving Wally installation makefile
2021-12-21 05:10:14 +00:00
David Harris
0c57b61ace
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:09:20 -08:00
David Harris
001c39d8eb
Fixing paths in wally-setup.sh
2021-12-20 21:08:34 -08:00
Ross Thompson
59252208a8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 21:26:48 -06:00
Ross Thompson
47638cdccf
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
David Harris
8072ed242c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-21 02:35:45 +00:00
David Harris
434f49c03e
Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead
2021-12-21 02:35:41 +00:00
Ross Thompson
d830721a11
Fixed Type 5b interaction between dcache and hptw.
...
This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
6aff6b0fa3
Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
2021-12-20 10:03:56 -06:00
Ross Thompson
53736096a6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
b261b18aa8
More signal name cleanup in LSU.
2021-12-19 22:47:48 -06:00
Ross Thompson
533c2f3556
Remove verbosity from lsu state machine.
2021-12-19 22:41:34 -06:00
Ross Thompson
82dd41a0fd
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
9c2fc30507
Signal renames.
2021-12-19 22:21:03 -06:00
Ross Thompson
2f5de7eb82
Hardware reductions in the lsu.
2021-12-19 22:00:28 -06:00
Ross Thompson
035ce99938
Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent.
2021-12-19 21:36:54 -06:00
Ross Thompson
30770db4ac
Removed lsuArb and placed remaining logic in lsu.sv.
...
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
2021-12-19 21:34:40 -06:00
Ross Thompson
019e300a14
Added file showing how to compile riscv toolchain for different extension combinations.
2021-12-19 20:31:55 -06:00
Ross Thompson
db76878581
Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card.
...
mv qemu patches to tests directory.
2021-12-19 20:11:32 -06:00
David Harris
193885c958
Moved generate of conditional units to hart
2021-12-19 17:03:57 -08:00
David Harris
1196e5c191
Moved generate statements for optional units into wallypipelinedhart
2021-12-19 16:53:41 -08:00
Ross Thompson
7b2f5440a5
Changes to buildroot to support MemAdrM to IEUAdrM name changes.
2021-12-19 18:24:40 -06:00
Ross Thompson
aeb8c94df1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-19 18:16:49 -06:00
Ross Thompson
cef4b6399d
Switched to using an always block for lsu stall logic. This avoids the problematic x propagation.
2021-12-19 18:16:08 -06:00
Ross Thompson
814bcec7b7
Implemented what I think is the last required change for the lsu state machine.
2021-12-19 17:57:12 -06:00
Ross Thompson
54fd8678b0
Created hack to get around imperas64mmu unknown (value = x) bug.
2021-12-19 17:53:13 -06:00
Ross Thompson
13f0e9bafa
Fixed bug where icache did not replay PCF on itlb miss.
2021-12-19 17:01:13 -06:00
Ross Thompson
04d0b85f96
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
2021-12-19 16:12:31 -06:00
David Harris
5e1c3e322b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-19 13:53:53 -08:00
David Harris
691c1c0dd0
ALUControl cleanup
2021-12-19 13:53:45 -08:00
Katherine Parry
ece9e9df84
fixed some small errors in FMA
2021-12-19 13:51:46 -08:00
Ross Thompson
202203904c
Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
2021-12-19 15:10:33 -06:00
Ross Thompson
9adcf86a40
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
...
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
620f4a58d4
Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states.
2021-12-19 13:55:57 -06:00
Ross Thompson
fdf493bd47
minro change. comments about needed changes in dcache.
2021-12-19 13:53:02 -06:00
