Ross Thompson
27f6f00402
Changes for xcelium.
2023-07-07 18:22:28 -05:00
Ross Thompson
9a49ec0b98
Removed duplicate signal name from testbench.
2023-07-07 16:34:08 -05:00
Ross Thompson
cb22463763
Fixed slight bug in config from parameterization.
2023-07-07 16:33:34 -05:00
Ross Thompson
235546fa06
Merge branch 'main' of github.com:ross144/cvw
2023-07-07 13:25:00 -05:00
Ross Thompson
cdf73d3b51
Updated comments.
2023-07-06 15:24:26 -05:00
Ross Thompson
e4555dc4af
Removed unused parameter.
2023-07-06 14:57:07 -05:00
Ross Thompson
2ce8b66574
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-07-06 14:55:43 -05:00
David Harris
369e8fb5ec
Removed outdated commment about endianness
2023-07-06 12:41:46 -07:00
David Harris
869a7cb827
Removed MTINST, which is not used in a system without a hypervisor
2023-07-06 12:40:53 -07:00
Ross Thompson
a963e50e88
It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga.
2023-07-06 14:07:37 -05:00
Ross Thompson
df56ff73c0
This is at least functionally correct, but has verilator lint issues.
2023-07-06 11:53:34 -05:00
Ross Thompson
c000366d3e
closer, but the wally32/64priv tests are failing.
2023-07-05 17:47:38 -05:00
Ross Thompson
98147e116a
Partially solved fpga boot.
2023-07-05 17:30:55 -05:00
Ross Thompson
6a2eca5657
Merge pull request #355 from davidharrishmc/dev
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Decoder improvements
2023-07-05 00:08:49 -04:00
David Harris
269bb688ea
Fixed comment typo
2023-07-04 11:34:58 -07:00
David Harris
b04763bcf2
Commented SVADU requirements for wally32priv mmu tests
2023-07-04 11:34:07 -07:00
David Harris
410ef01627
fixed spacing in fdivsqrt
2023-07-04 11:27:36 -07:00
David Harris
001d3cfdc5
Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder
2023-07-02 13:29:27 -07:00
David Harris
afe66d0ee4
Added prefetch instructions; sent cbo instructions to LSU
2023-07-02 10:55:35 -07:00
David Harris
723b8266cb
Added prefetch signals
2023-07-02 10:06:58 -07:00
David Harris
482e4e6e92
Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions
2023-07-02 09:35:05 -07:00
David Harris
c48283801a
Fixed csr typos
2023-07-02 02:01:40 -07:00
David Harris
61208e486c
Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode
2023-07-02 02:00:27 -07:00
David Harris
b6ae5661b4
Added environment configuration control (menvcfg/senvcfg) of cbo instructions
2023-07-02 01:52:25 -07:00
David Harris
15314a9c9a
Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
2023-07-02 00:34:30 -07:00
David Harris
41e9f20943
improved decoder checking atomic and RW and MW and privileged instructions
2023-07-02 00:02:03 -07:00
David Harris
e34ef4d636
improved decoder checking atomic instructions
2023-07-01 23:10:57 -07:00
David Harris
d930be332e
Improved instruction decoding for illegal floating-point loads/stores and fences
2023-07-01 22:48:04 -07:00
Ross Thompson
a8cdcaa26b
Merge pull request #352 from stineje/main
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Change to testbench-fp.sv
2023-06-29 11:30:01 -04:00
James E. Stine
67fdeae9c9
Add reset to wave window
2023-06-29 08:47:16 -05:00
James E. Stine
48bec40902
Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion.
2023-06-29 08:46:11 -05:00
Ross Thompson
c6a55c446a
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-27 11:04:27 -05:00
Ross Thompson
cc5d8fbf06
Updates for fpga.
2023-06-27 11:04:20 -05:00
Ross Thompson
b1203b5460
Merge pull request #350 from stineje/main
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Minor tweak to fix vectors not working for fadd.
2023-06-26 16:41:01 -04:00
James E. Stine
3cfec29cc7
Minor tweak to fix vectors not working for fadd.
2023-06-26 14:25:44 -05:00
Ross Thompson
1a936882f8
Merge pull request #349 from stineje/main
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Modification to testbench-fp.sv
2023-06-26 12:51:57 -04:00
James E. Stine
dd6b12c6dc
Add signals for ResMatch & CheckNow to sim window that are related to TestFloat operation
2023-06-26 10:15:46 -05:00
James E. Stine
786329b11d
Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly
2023-06-26 10:14:49 -05:00
David Harris
717c22a5d1
Merge pull request #348 from stineje/main
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Modify testfloat-fp.sv for parameterization
2023-06-22 13:33:29 -07:00
James E. Stine
97b1c01dc0
Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works
2023-06-22 15:27:17 -05:00
James E. Stine
0b7b28c2f0
For some reason this was modified - I probably made a mistake - put back vsim
2023-06-22 15:26:22 -05:00
James E. Stine
1f63e6d483
Remove path for cvw.sv so its found
2023-06-22 15:25:56 -05:00
Ross Thompson
7aecd72c35
Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits.
2023-06-22 12:55:49 -05:00
Ross Thompson
7550fd4bd9
Merge pull request #347 from kipmacsaigoren/unified_f_int_gen_fix
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fixed bug in combined intdivrem testvector extract script
2023-06-22 12:38:45 -04:00
Kevin Kim
f6a3474550
fixed bug in testvector extract script
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-old script skips first 2 lines in rv32m case, new script only skips first line
- prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer
- prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file)
2023-06-22 09:13:22 -07:00
Ross Thompson
0c924b0cac
Merge pull request #346 from VictorClements/main
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FreeRTOS kernel submodule addin
2023-06-21 18:26:42 -04:00
Victor Clements
1dfb2ae9e9
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-06-21 09:02:02 -07:00
Ross Thompson
55a0ccbbc9
Merge pull request #345 from stineje/main
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Update sim-testfloat to fix errors due to bad config element. I am n…
2023-06-20 18:29:24 -04:00
James E. Stine
66643eb78e
Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file
2023-06-20 17:26:54 -05:00
Ross Thompson
a8f11dcad0
FPGA updates.
2023-06-20 11:11:34 -05:00
