mirror of
https://github.com/openhwgroup/cvw
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Merge pull request #350 from stineje/main
Minor tweak to fix vectors not working for fadd.
This commit is contained in:
Ross Thompson
GitHub
commit
b1203b5460
@ -2,7 +2,7 @@
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//
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// Written: me@KatherineParry.com, james.stine@okstate.edu
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//
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// Purpose: Testbench for Testfloat
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// Purpose: Testbench for UCB Testfloat on Wally
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//
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// A component of the Wally configurable RISC-V project.
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//
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@ -21,18 +21,21 @@
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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//`include "wally-config.vh"
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`include "config.vh"
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`include "tests-fp.vh"
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import cvw::*;
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module testbenchfp;
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// Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
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// to run specific precisions (e.g., quad or all)
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parameter TEST="none";
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parameter TEST_SIZE="none";
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`include "parameter-defs.vh"
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// FIXME: needs cleaning of unused variables (jes)
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string Tests[]; // list of tests to be run
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logic [2:0] OpCtrl[]; // list of op controls
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logic [2:0] Unit[]; // list of units being tested
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@ -61,7 +64,8 @@ module testbenchfp;
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logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
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logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
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logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit
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logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
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logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags
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logic [4:0] CmpFlg; // Outputed flags
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logic AnsNaN, ResNaN, NaNGood;
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logic Xs, Ys, Zs; // sign of the inputs
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logic [P.NE-1:0] Xe, Ye, Ze; // exponent of the inputs
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@ -72,7 +76,7 @@ module testbenchfp;
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logic XInf, YInf, ZInf; // is the input infinity
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logic XZero, YZero, ZZero; // is the input zero
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logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
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logic [P.CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
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logic [P.CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
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logic IntZero;
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logic CvtResSgnE;
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logic [P.NE:0] CvtCalcExpE; // the calculated exponent
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@ -114,8 +118,8 @@ module testbenchfp;
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logic [P.NE+1:0] QeM;
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logic [P.DIVb:0] QmM;
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logic [P.XLEN-1:0] FIntDivResultM;
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logic ResMatch; // Check if result matches
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logic FlagMatch; // Check if flag matches
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logic ResMatch; // Check if result match
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logic FlagMatch; // Check if IEEE flags match
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logic CheckNow; // Final check
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///////////////////////////////////////////////////////////////////////////////////////////////
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@ -139,6 +143,7 @@ module testbenchfp;
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// all - test all of the above
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initial begin
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// Information displayed for user on what is simulating
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$display("\nThe start of simulation...");
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$display("This simulation for TEST is %s", TEST);
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$display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
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@ -168,7 +173,7 @@ module testbenchfp;
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end
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// if the floating-point conversions are being tested
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if (TEST === "cvtfp" | TEST === "all") begin
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if(P.D_SUPPORTED) begin // if double precision is supported
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if (P.D_SUPPORTED) begin // if double precision is supported
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// add the 128 <-> 64 bit conversions to the to-be-tested list
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Tests = {Tests, f128f64cvt};
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// add the op-ctrls (i.e. the format of the result)
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@ -184,7 +189,7 @@ module testbenchfp;
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Fmt = {Fmt, 2'b01};
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end
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end
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if(P.F_SUPPORTED) begin // if single precision is supported
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if (P.F_SUPPORTED) begin // if single precision is supported
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// add the 128 <-> 32 bit conversions to the to-be-tested list
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Tests = {Tests, f128f32cvt};
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// add the op-ctrls (i.e. the format of the result)
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@ -200,7 +205,7 @@ module testbenchfp;
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Fmt = {Fmt, 2'b00};
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end
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end
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if(P.ZFH_SUPPORTED) begin // if half precision is supported
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if (P.ZFH_SUPPORTED) begin // if half precision is supported
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// add the 128 <-> 16 bit conversions to the to-be-tested list
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Tests = {Tests, f128f16cvt};
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// add the op-ctrls (i.e. the format of the result)
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@ -311,7 +316,7 @@ module testbenchfp;
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end
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end
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if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested
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if(P.F_SUPPORTED) begin // if single precision is supported
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if (P.F_SUPPORTED) begin // if single precision is supported
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// add the 64 <-> 32 bit conversions to the to-be-tested list
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Tests = {Tests, f64f32cvt};
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// add the op-ctrls (i.e. the format of the result)
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@ -327,7 +332,7 @@ module testbenchfp;
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Fmt = {Fmt, 2'b00};
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end
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end
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if(P.ZFH_SUPPORTED) begin // if half precision is supported
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if (P.ZFH_SUPPORTED) begin // if half precision is supported
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// add the 64 <-> 16 bit conversions to the to-be-tested list
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Tests = {Tests, f64f16cvt};
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// add the op-ctrls (i.e. the format of the result)
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@ -438,7 +443,7 @@ module testbenchfp;
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end
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end
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if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested
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if(P.ZFH_SUPPORTED) begin
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if (P.ZFH_SUPPORTED) begin
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// add the 32 <-> 16 bit conversions to the to-be-tested list
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Tests = {Tests, f32f16cvt};
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// add the op-ctrls (i.e. the format of the result)
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@ -618,7 +623,6 @@ module testbenchfp;
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end
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end
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end
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// check if nothing is being tested
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if (Tests.size() == 0) begin
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$display("TEST %s not supported in this configuration", TEST);
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@ -644,7 +648,7 @@ module testbenchfp;
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string tt0;
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tt0 = $psprintf("%s", Tests[TestNum]);
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testname = {p, tt0};
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//$display("Here you are %s", testname);
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$display("Here you are %s", testname);
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$display("\n\nRunning %s vectors ", Tests[TestNum]);
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$readmemh(testname, TestVectors);
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// set the test index to 0
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@ -662,7 +666,7 @@ module testbenchfp;
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// - 1 for the larger precision
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// - 0 for the smaller precision
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always_comb begin
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if(P.FMTBITS == 1) ModFmt = FmtVal == P.FMT;
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if (P.FMTBITS == 1) ModFmt = FmtVal == P.FMT;
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else ModFmt = FmtVal;
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end
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@ -722,6 +726,7 @@ module testbenchfp;
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.Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
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.XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
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end
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if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
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fdivsqrt #(P) fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym),
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.XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
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@ -765,7 +770,7 @@ module testbenchfp;
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// Check if the correct answer and result is a NaN
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always_comb begin
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if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin
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if (UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin
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// an integer output can't be a NaN
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AnsNaN = 1'b0;
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ResNaN = 1'b0;
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@ -818,7 +823,7 @@ module testbenchfp;
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`FMAUNIT: Res = FpRes;
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`DIVUNIT: Res = FpRes;
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`CMPUNIT: Res = CmpRes;
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`CVTINTUNIT: if(WriteIntVal) Res = IntRes; else Res = FpRes;
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`CVTINTUNIT: if (WriteIntVal) Res = IntRes; else Res = FpRes;
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`CVTFPUNIT: Res = FpRes;
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endcase
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@ -836,13 +841,35 @@ module testbenchfp;
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OldFDivBusyE = FDivDoneE;
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// For FP division this adds extra clock cycles to make sure the
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// computation completes. 18 clocks cycles are utilize to handle
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// Quad, but this can be changed for each precision to go faster.
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// computation completes.
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always @(posedge clk) begin
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// Add extra clock cycles in beginning for fdivsqrt to adequate reset state
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if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin
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repeat (18)
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@(posedge clk);
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if (~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin
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// This allows specific number of clocks to allow each vector
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// to complete for division or square root. It is an
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// arbitrary value and can be changed, if needed.
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case (FmtVal)
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// QP
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4'b11: begin
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repeat (20)
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@(posedge clk);
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end
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// HP
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4'b10: begin
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repeat (14)
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@(posedge clk);
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end
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// DP
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4'b01: begin
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repeat (18)
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@(posedge clk);
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end
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// SP
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4'b00: begin
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repeat (16)
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@(posedge clk);
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end
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endcase // case (FmtVal)
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if (reset != 1'b1)
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VectorNum += 1; // increment the vector
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end
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@ -850,7 +877,6 @@ module testbenchfp;
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// check results on falling edge of clk
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always @(negedge clk) begin
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// check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify:
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// - the sign of the NaN does not matter for the opperations being tested
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// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
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@ -935,10 +961,11 @@ module testbenchfp;
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// Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but
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// the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
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else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) |
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(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) |
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(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) |
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(~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
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else if ((UnitVal === `CVTINTUNIT) &
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~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) |
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(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) |
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(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) |
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(~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
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errors += 1;
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$display("There is an error in %s", Tests[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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@ -955,17 +982,15 @@ module testbenchfp;
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// set the vector index back to 0
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VectorNum = 0;
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// incemet the operation if all the rounding modes have been tested
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if(FrmNum === 4) OpCtrlNum += 1;
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if (FrmNum === 4) OpCtrlNum += 1;
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// increment the rounding mode or loop back to rne
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if(FrmNum < 4) FrmNum += 1;
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if (FrmNum < 4) FrmNum += 1;
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else FrmNum = 0;
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// if no more Tests - finish
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if(Tests[TestNum] === "") begin
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if (Tests[TestNum] === "") begin
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$display("\nAll Tests completed with %d errors\n", errors);
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$stop;
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end
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$display("Running %s vectors", Tests[TestNum]);
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end
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end
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@ -1000,105 +1025,108 @@ module readvectors (
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localparam Q_LEN = 32'd128;
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`include "parameter-defs.vh"
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logic XEn, YEn, ZEn;
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logic XEn;
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logic YEn;
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logic ZEn;
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logic FPUActive;
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// apply test vectors on rising edge of clk
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// Format of vectors Inputs(1/2/3)_AnsFlg
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always @(VectorNum) begin
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// Initial delay is given to allow vector to work for fdiv
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// otherwise it will fail on first vector - fix needed (jes)
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DivStart = 1'b0;
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#20;
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#1;
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AnsFlg = TestVector[4:0];
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DivStart = 1'b0;
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case (Unit)
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`FMAUNIT:
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case (Fmt)
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2'b11: begin // quad
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if(OpCtrl === `FMA_OPCTRL) begin
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2'b11: begin // quad
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if (OpCtrl === `FMA_OPCTRL) begin
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X = TestVector[8+4*(P.Q_LEN)-1:8+3*(P.Q_LEN)];
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Y = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
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Z = TestVector[8+2*(P.Q_LEN)-1:8+P.Q_LEN];
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end
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else begin
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X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
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if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; else Y = {2'b0, {P.Q_NE-1{1'b1}}, (P.Q_NF)'(0)};
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if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
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if (OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; else Y = {2'b0, {P.Q_NE-1{1'b1}}, (P.Q_NF)'(0)};
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if (OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
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end
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Ans = TestVector[8+(P.Q_LEN-1):8];
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end
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2'b01: if (P.D_SUPPORTED)begin // double
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if(OpCtrl === `FMA_OPCTRL) begin
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2'b01: if (P.D_SUPPORTED) begin // double
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if (OpCtrl === `FMA_OPCTRL) begin
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]};
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Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
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Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]};
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end
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else begin
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
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if(OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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else Y = {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)};
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if(OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}};
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if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}};
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else Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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end
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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end
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2'b00: if (P.S_SUPPORTED)begin // single
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if(OpCtrl === `FMA_OPCTRL) begin
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2'b00: if (P.S_SUPPORTED) begin // single
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if (OpCtrl === `FMA_OPCTRL) begin
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]};
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Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
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Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]};
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end
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else begin
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
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if(OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
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if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
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else Y = {{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)};
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if(OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}};
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if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}};
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else Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
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end
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
if(OpCtrl === `FMA_OPCTRL) begin
|
||||
2'b10: begin // half
|
||||
if (OpCtrl === `FMA_OPCTRL) begin
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]};
|
||||
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]};
|
||||
end
|
||||
else begin
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
if(OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
else Y = {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)};
|
||||
if(OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}};
|
||||
if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}};
|
||||
else Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
end
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
`DIVUNIT:
|
||||
if(OpCtrl[0])
|
||||
if (OpCtrl[0])
|
||||
case (Fmt)
|
||||
2'b11: begin // quad
|
||||
2'b11: begin // quad
|
||||
#20;
|
||||
X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
if (~clk) #5;
|
||||
DivStart = 1'b1; #10 // one clk cycle
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED)begin // double
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
#20;
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
if (~clk) #5;
|
||||
DivStart = 1'b1; #10
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED)begin // single
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
#20;
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
if (~clk) #5;
|
||||
DivStart = 1'b1; #10
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b10: begin // half
|
||||
2'b10: begin // half
|
||||
#20;
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
if (~clk) #5;
|
||||
@ -1108,7 +1136,8 @@ module readvectors (
|
||||
endcase
|
||||
else
|
||||
case (Fmt)
|
||||
2'b11: begin // quad
|
||||
2'b11: begin // quad
|
||||
#20;
|
||||
X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
|
||||
Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
@ -1116,7 +1145,8 @@ module readvectors (
|
||||
DivStart = 1'b1; #10 // one clk cycle
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED)begin // double
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
#20;
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
|
||||
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
@ -1124,7 +1154,8 @@ module readvectors (
|
||||
DivStart = 1'b1; #10
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED)begin // single
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
#20;
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
|
||||
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
@ -1132,7 +1163,8 @@ module readvectors (
|
||||
DivStart = 1'b1; #10
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b10: begin // half
|
||||
2'b10: begin // half
|
||||
#20;
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
@ -1143,22 +1175,22 @@ module readvectors (
|
||||
endcase
|
||||
`CMPUNIT:
|
||||
case (Fmt)
|
||||
2'b11: begin // quad
|
||||
2'b11: begin // quad
|
||||
X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)];
|
||||
Y = TestVector[12+(P.Q_LEN)-1:12];
|
||||
Ans = TestVector[8];
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED)begin // double
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]};
|
||||
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
|
||||
Ans = TestVector[8];
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED)begin // single
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
|
||||
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
|
||||
Ans = TestVector[8];
|
||||
end
|
||||
2'b10: begin // half
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]};
|
||||
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]};
|
||||
Ans = TestVector[8];
|
||||
@ -1166,188 +1198,187 @@ module readvectors (
|
||||
endcase
|
||||
`CVTFPUNIT:
|
||||
case (Fmt)
|
||||
2'b11: begin // quad
|
||||
2'b11: begin // quad
|
||||
case (OpCtrl[1:0])
|
||||
2'b11: begin // quad
|
||||
2'b11: begin // quad
|
||||
X = {TestVector[8+P.Q_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED)begin // double
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {TestVector[8+P.Q_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: begin // single
|
||||
2'b00: begin // single
|
||||
X = {TestVector[8+P.Q_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
2'b10: begin // half
|
||||
X = {TestVector[8+P.Q_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED)begin // double
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
case (OpCtrl[1:0])
|
||||
2'b11: begin // quad
|
||||
2'b11: begin // quad
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: begin // double
|
||||
2'b01: begin // double
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: begin // single
|
||||
2'b00: begin // single
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED)begin // single
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
case (OpCtrl[1:0])
|
||||
2'b11: begin // quad
|
||||
2'b11: begin // quad
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED)begin // double
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: begin // single
|
||||
2'b00: begin // single
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b10: begin // half
|
||||
2'b10: begin // half
|
||||
case (OpCtrl[1:0])
|
||||
2'b11: begin // quad
|
||||
2'b11: begin // quad
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED)begin // double
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED)begin // single
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
|
||||
endcase
|
||||
`CVTINTUNIT:
|
||||
case (Fmt)
|
||||
2'b11: begin // quad
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
2'b11: begin // quad
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
casex ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> quad
|
||||
2'b11: begin // long -> quad
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)];
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b10: begin // int -> quad
|
||||
2'b10: begin // int -> quad
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: begin // quad -> long
|
||||
2'b01: begin // quad -> long
|
||||
X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
||||
end
|
||||
2'b00: begin // quad -> int
|
||||
2'b00: begin // quad -> int
|
||||
X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
// {Int->Fp?, is the integer a long}
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
// {Int->Fp?, is the integer a long}
|
||||
casex ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> double
|
||||
2'b11: begin // long -> double
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)];
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // int -> double
|
||||
2'b10: begin // int -> double
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b01: begin // double -> long
|
||||
2'b01: begin // double -> long
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
||||
end
|
||||
2'b00: begin // double -> int
|
||||
2'b00: begin // double -> int
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED)begin // single
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
casex ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> single
|
||||
2'b11: begin // long -> single
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)];
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // int -> single
|
||||
2'b10: begin // int -> single
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b01: begin // single -> long
|
||||
2'b01: begin // single -> long
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
||||
end
|
||||
2'b00: begin // single -> int
|
||||
2'b00: begin // single -> int
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b10: begin // half
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
2'b10: begin // half
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
casex ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> half
|
||||
2'b11: begin // long -> half
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // int -> half
|
||||
2'b10: begin // int -> half
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
2'b01: begin // half -> long
|
||||
2'b01: begin // half -> long
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
||||
end
|
||||
2'b00: begin // half -> int
|
||||
2'b00: begin // half -> int
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user