Ross Thompson
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abc79c6c8e
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Possible improvement to cache which removes the cpu_busy states.
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2022-07-22 23:20:37 -05:00 |
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Ross Thompson
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1cad05fef9
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Minor cleanup of cache.
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2022-07-19 23:04:23 -05:00 |
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Ross Thompson
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8698799077
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Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
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2022-07-19 22:42:25 -05:00 |
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Ross Thompson
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a79e5e11f6
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Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
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2022-07-18 23:37:18 -05:00 |
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Ross Thompson
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0ef6137ab9
|
Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
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2022-07-17 21:05:31 -05:00 |
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Ross Thompson
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8356e5d742
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Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
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2022-07-17 16:20:04 -05:00 |
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David Harris
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622773343f
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restored intPending logic to be sticky for PLIC
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2022-07-16 17:43:31 -07:00 |
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Katherine Parry
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e3ed40620c
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forgot some files
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2022-07-15 21:42:45 +00:00 |
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Katherine Parry
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304c81eb17
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-15 20:17:08 +00:00 |
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Katherine Parry
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5cb9c9f319
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merged floating-point radix-2 divider with radix-4
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2022-07-15 20:16:59 +00:00 |
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cturek
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8c57eca262
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Square root radix 2 working, does not work with division
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2022-07-14 22:52:09 +00:00 |
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cturek
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2f96989aab
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Square root
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2022-07-14 21:19:45 +00:00 |
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cturek
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cabd41a5a0
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Six tests passing and a bunch of sizizing issues fixed
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2022-07-14 19:38:27 +00:00 |
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Katherine Parry
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83cc429700
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-14 18:16:13 +00:00 |
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Katherine Parry
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2fe8b6e34c
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fixed error in divsqrt
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2022-07-14 18:16:00 +00:00 |
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cturek
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8f7ffc3f29
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S and SM are updating but are not correct yet
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2022-07-14 00:39:30 +00:00 |
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Katherine Parry
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66bef379cb
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renamed a file to fit diagram
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2022-07-13 23:44:54 +00:00 |
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cturek
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0b91e7526f
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DIVLEN and counter updated for sqrt computation and rounding
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2022-07-13 22:42:39 +00:00 |
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Katherine Parry
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3dcddf8453
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some code cleanup
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2022-07-13 15:28:22 -07:00 |
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Katherine Parry
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b874c5c05d
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removed minus 1 case in rounding
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2022-07-13 15:01:38 -07:00 |
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cturek
|
97a1548356
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radix 4 files removed from srt and divlen modified for sqrt
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2022-07-13 19:46:48 +00:00 |
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cturek
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b1906399aa
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Lint error fixed and added comments to preprocessing
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2022-07-13 19:34:04 +00:00 |
|
cturek
|
5975d0d470
|
Testbench accepts standard test vector files
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2022-07-13 18:30:18 +00:00 |
|
cturek
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3ed6b8d1ff
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Test generation files in common format
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2022-07-13 18:11:13 +00:00 |
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cturek
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120994b42b
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Finalized sqrt, ready for debugging
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2022-07-13 17:56:23 +00:00 |
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cturek
|
6e96ca2c9b
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Added adder input selection to on the fly converter
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2022-07-13 17:47:27 +00:00 |
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cturek
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e9ce71ca20
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-13 17:36:56 +00:00 |
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Katherine Parry
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b45b3baec2
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removed the +1 in the cvt
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2022-07-13 09:41:35 -07:00 |
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Katherine Parry
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3c1bea1104
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removed warnings and took a mux out of the critical path
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2022-07-12 18:32:17 -07:00 |
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cturek
|
8d5081e8e9
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little fix
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2022-07-12 23:04:33 +00:00 |
|
cturek
|
b505ef135d
|
Square root implemented
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2022-07-12 22:45:54 +00:00 |
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Katherine Parry
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12a54161c0
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found the bug in the store modification
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2022-07-12 22:42:19 +00:00 |
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Katherine Parry
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18d7fee541
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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cturek
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8edf44063a
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C register and other various fixes
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2022-07-12 22:18:56 +00:00 |
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cturek
|
c60991f2bf
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On the fly conversion for square root
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2022-07-12 02:21:38 +00:00 |
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Katherine Parry
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1267d33d3c
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forgot a file
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2022-07-11 18:31:51 -07:00 |
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Katherine Parry
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ba339fc794
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-11 18:30:29 -07:00 |
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Katherine Parry
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bea4ec078d
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variable interations implemented in radix-4 divider
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2022-07-11 18:30:21 -07:00 |
|
DTowersM
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fe7d03a3da
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added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
|
2022-07-11 21:13:09 +00:00 |
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David Harris
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03a20610aa
|
added comment about checking SRAM size
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2022-07-10 12:48:51 +00:00 |
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David Harris
|
d1a7832dd9
|
added comment about RAMs in cacheway
|
2022-07-10 12:47:34 +00:00 |
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Katherine Parry
|
62205ebb3b
|
renamed FLoad2 to FStore2
|
2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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97e7e619d9
|
moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
|
cturek
|
0dc30a0acf
|
F Selection
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2022-07-08 21:53:52 +00:00 |
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Katherine Parry
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c56fdd7e0f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-08 12:30:50 -07:00 |
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Katherine Parry
|
88b4f9b40a
|
renamed signals in cvt and prostproc
|
2022-07-08 12:30:43 -07:00 |
|
James Stine
|
99fed5d59f
|
Update SRAM to /proj/wally
|
2022-07-08 08:09:55 -05:00 |
|
David Harris
|
8be1dafbd6
|
Removed testbench code that ignores mismatch on zero signatures
|
2022-07-08 09:17:31 +00:00 |
|
David Harris
|
87ea95e6c5
|
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-08 09:09:07 +00:00 |
|
David Harris
|
5ae88dbef0
|
Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
|
2022-07-08 09:09:02 +00:00 |
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