naichewa
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3b7661dfd5
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SckDiv Zero bug fixes
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2024-09-03 14:58:46 -07:00 |
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Jacob Pease
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d8b75440b6
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With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
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2024-08-20 16:24:37 -05:00 |
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David Harris
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b3661a0af4
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Removed unused WALLY-lrsc reference outputs that were incorrect and are not used because Sail is the reference instead
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2024-03-24 12:31:49 -07:00 |
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David Harris
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9ff9f9e0ae
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Updated wally-riscv-arch-test to be able to compile zfh and zfa tests. This caused a change in startup code, so certain reference_output results needed to change to compensate. Also commented out fcvtmod test in Zfa that fails because Sail produces the wrong expected value.
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2024-03-14 19:03:57 -07:00 |
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David Harris
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824bc0dab7
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Fixed expected value on WALLY-satp-invalid
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2024-02-16 11:12:57 -08:00 |
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Rose Thompson
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b04ad23c33
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Fixed bugs in the wally64periph signature.
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2023-12-19 16:16:59 -06:00 |
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Rose Thompson
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726efee1e2
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Fixed bugs in the cbom test.
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2023-12-19 15:53:48 -06:00 |
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Rose Thompson
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418ae0decc
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Fixed some regression tests with David's help.
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2023-12-19 14:18:21 -06:00 |
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David Harris
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166c98b6f6
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Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn
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2023-12-13 19:43:17 -08:00 |
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Rose Thompson
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9dfe421c55
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Yay! Zicclsm passes my regression test now.
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2023-11-10 18:28:51 -06:00 |
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Rose Thompson
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c0e02ae190
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Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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02ab9fe99c
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Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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bd866e1025
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Fixed some more bugs in the Zicclsm signature.
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2023-11-10 17:36:10 -06:00 |
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Rose Thompson
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b74bfbeefd
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
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naichewa
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a5837eb62c
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
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naichewa
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4651b807ed
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added test cases
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2023-11-02 15:43:08 -07:00 |
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Rose Thompson
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0a4ed5515b
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Merge branch 'main' into Zicclsm
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2023-11-02 12:55:51 -05:00 |
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Rose Thompson
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afa1d85e3b
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Doesn't yet fully work.
Thomas is going to finish debugging while I'm on the RISCV summit next week.
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2023-11-02 12:07:42 -05:00 |
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Rose Thompson
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7ba891f607
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Progress. I think the remaining bugs are in the regression test's signature.
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2023-11-01 17:51:48 -05:00 |
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Rose Thompson
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5660eff57d
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Working through issues with the psill logic.
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2023-10-31 18:50:13 -05:00 |
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Rose Thompson
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4984b3935f
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Progress
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2023-10-31 14:50:33 -05:00 |
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Rose Thompson
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c061440141
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First stab at the misaligned test.
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2023-10-31 12:30:10 -05:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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2330f4ee63
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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Rose Thompson
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2241976d29
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Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
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2023-10-30 18:26:11 -05:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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naichewa
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0ff9ce527d
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Merge branch 'main' into spi
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2023-10-16 22:59:50 -07:00 |
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David Harris
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ac4216b43d
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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David Harris
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6245748ed7
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Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
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2023-10-15 15:31:03 -07:00 |
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David Harris
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434d6b2c5c
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minfo test working again with mconfigptr for RV64
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2023-10-15 06:41:52 -07:00 |
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naichewa
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aa5abfc8e8
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always working after reg bit swizzle changes
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2023-10-13 14:22:32 -07:00 |
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naichewa
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d5d4f9d044
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transferred spi changes in ECA-authorized commit
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2023-10-12 13:36:57 -07:00 |
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David Harris
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d526d28804
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Added MENVCFG.HADE bit and updated SVADU to depend on this bit
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2023-10-04 09:34:28 -07:00 |
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Ross Thompson
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12c3c98824
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Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.
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2023-08-30 11:29:44 -05:00 |
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David Harris
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8d3ff59673
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Completed basic tests of svnapot and svpbmt
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2023-08-28 06:57:35 -07:00 |
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Ross Thompson
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914b6f9734
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Now have CBOZ instructions working!
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2023-08-24 16:47:35 -05:00 |
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Ross Thompson
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310b700550
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Have a working 32 bit cbom test!
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2023-08-21 13:46:09 -05:00 |
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Ross Thompson
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d4c6ba627d
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Working CBO tests for 64 bit!
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2023-08-21 12:55:07 -05:00 |
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Ross Thompson
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5ed096e4bc
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Made a bunch of progress towards getting cbo instructions tested.
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2023-08-21 11:46:21 -05:00 |
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David Harris
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c137a1c8cf
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Fixed timer interrupt testing
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2023-06-09 17:20:41 -07:00 |
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David Harris
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b70b0c7c5e
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Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
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2023-06-09 14:40:01 -07:00 |
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Kip Macsai-Goren
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34200e8c76
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restored original virt mem tests when svadu is not supported
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2023-04-11 18:47:08 -07:00 |
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Kip Macsai-Goren
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c4766c8a02
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renamed virt mem tests to include svadu
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2023-04-11 18:46:37 -07:00 |
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Kip Macsai-Goren
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b2d6084eea
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removed unnecessary 'deadbeef's at the end of reference outputs
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2023-04-11 18:32:04 -07:00 |
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Kip Macsai-Goren
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a82c0a7780
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Modified virt mem tests to do correct r/w when svadu is enabled
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2023-04-11 18:08:30 -07:00 |
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Kip Macsai-Goren
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e0b938b409
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Removed Trap outputs from writes covered by SVADU
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2023-04-11 17:41:57 -07:00 |
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Kip Macsai-Goren
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2e151b6b08
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updated tests to reflect non-writeable bits of deleg
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2023-03-29 15:24:00 -07:00 |
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David Harris
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2e5c50e24a
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Fixed RV32 tests after PMP fix
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2023-03-28 08:35:23 -07:00 |
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Kip Macsai-Goren
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106ed02a7e
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Revert "added premilinary boundary ccrossing cases"
This reverts commit 7870148814.
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2023-03-24 11:27:41 -07:00 |
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Kip Macsai-Goren
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ff59fefcc9
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replaced inerrupt tests with allowed versions
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2023-03-24 11:22:39 -07:00 |
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