James E. Stine
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a60e19dc3f
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Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking
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2021-10-22 13:41:50 -05:00 |
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Katherine Parry
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00cc1e0c5c
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put the FMA priority encoders into their own module
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2021-10-22 10:03:12 -07:00 |
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James E. Stine
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0e0a107a98
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Get rid of lint warning - still need more testing though
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2021-10-21 15:19:22 -05:00 |
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James E. Stine
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49721a169b
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Clean up some FPU and add pipelined fpdivsqrt to fpu.sv
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2021-10-21 13:52:12 -05:00 |
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James E. Stine
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129ef03b2d
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Fix fpdivsqrt lint error on CPA for convergence
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2021-10-20 17:46:13 -05:00 |
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David Harris
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687703f0d8
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removed .* from wallypipeliendsoc
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2021-10-20 13:49:18 -07:00 |
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davidharrishmc
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923d03f657
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Update README.md
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2021-10-20 10:49:41 -07:00 |
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kipmacsaigoren
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742480d27d
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Fixed path to src and config files, added mdu timing reports
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2021-10-20 12:41:14 -05:00 |
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kipmacsaigoren
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b2deedd4b4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-20 12:15:53 -05:00 |
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kipmacsaigoren
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f0cf8bf17e
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Removed historical outputs from repo
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2021-10-20 12:15:40 -05:00 |
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James E. Stine
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7536e0a2ee
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Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
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2021-10-20 12:00:41 -05:00 |
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David Harris
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4aeadaacf0
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moved coemark and testsBP to tests
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2021-10-20 09:10:06 -07:00 |
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David Harris
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55fbafec74
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moved imperas-riscv-tests to tests
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2021-10-20 09:07:46 -07:00 |
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David Harris
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0e4f6392d6
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Move tests into subdirectory and moved wavedrom out of project
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2021-10-20 09:03:21 -07:00 |
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David Harris
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15e3b36a75
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-19 14:08:24 -07:00 |
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David Harris
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8747791bb8
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radix 2 SRT checkin
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2021-10-19 14:08:16 -07:00 |
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bbracker
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ca61d9b6b8
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gitignore the addins folder because it contains external repos
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2021-10-19 13:32:26 -07:00 |
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James E. Stine
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ed179b0bd9
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Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this
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2021-10-19 12:09:43 -05:00 |
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James E. Stine
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b65a4bd040
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Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).
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2021-10-19 11:58:06 -05:00 |
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David Harris
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8d08ca6a1e
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Changed some flops to settable
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2021-10-18 17:05:29 -07:00 |
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David Harris
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965946cae3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-18 16:54:08 -07:00 |
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David Harris
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df0b65e483
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replaced flopenl with flopenr when clearing to 0
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2021-10-18 16:53:18 -07:00 |
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davidharrishmc
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83af0740b5
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Update README.md
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2021-10-18 16:23:22 -07:00 |
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David Harris
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d0b9ebd2ef
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-18 15:44:31 -07:00 |
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David Harris
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47f7a5db9c
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Fixed multiplier and pointed arch tests to new path in addins
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2021-10-18 15:43:59 -07:00 |
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Ross Thompson
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83a76ffb0c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-18 17:25:48 -05:00 |
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Ross Thompson
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d8d414665c
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fixed issues with dc shell not liking modules with parameters without default values.
|
2021-10-18 17:24:15 -05:00 |
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davidharrishmc
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b8a126f311
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Update README.md
|
2021-10-18 13:43:10 -07:00 |
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davidharrishmc
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091d8550d0
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Update README.md
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2021-10-18 13:39:40 -07:00 |
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davidharrishmc
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d1d4f9dc5f
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Update README.md
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2021-10-18 11:17:24 -07:00 |
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davidharrishmc
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5ceb7f1308
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Update README.md
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2021-10-18 09:52:40 -07:00 |
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James E. Stine
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d895fd7ee5
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Sanitization some more on mult_cs.sv
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2021-10-18 05:24:16 -05:00 |
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James E. Stine
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aafa988ca2
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Update some on mult_cs and delete DW02_mult.v
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2021-10-18 05:06:49 -05:00 |
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James E. Stine
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5a1835622c
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Add hacky hand-made carry/save multiplier - will improve
|
2021-10-16 10:37:29 -05:00 |
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Katherine Parry
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33e5a078bf
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cvtfp module documented
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2021-10-14 15:25:31 -07:00 |
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James E. Stine
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6b30adb309
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Clean up some signals - beautification onging
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2021-10-14 17:12:00 -05:00 |
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Kip Macsai-Goren
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ffcf5f5825
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Fixed typo in imperas64mmu tests causing PMP tests not to run.
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2021-10-14 13:42:24 -07:00 |
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Skylar Litz
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395e070917
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-13 15:38:32 -07:00 |
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Skylar Litz
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d639222519
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add StallM signal back to DivStartE control
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2021-10-13 15:34:40 -07:00 |
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James E. Stine
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eb64a7f0c9
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Update to fpdivsqrt to go on posedge as it should. Also an update to
individual regression test for TestFloat (still needs some tweaking)
|
2021-10-13 17:14:42 -05:00 |
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kipmacsaigoren
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d5ed6059c7
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added outputs from synth run to test mul changes
|
2021-10-13 12:38:14 -05:00 |
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bbracker
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f2cab415b2
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gitignore new logs folder
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2021-10-12 10:42:13 -07:00 |
|
bbracker
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886a650da4
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change infrastructure to expect only 6.3 million from buildroot
|
2021-10-12 10:41:15 -07:00 |
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Shreya Sanghai
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d783acbbc5
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added DESIGN_COMPLIER to forgotten config files
|
2021-10-12 10:14:04 -07:00 |
|
Katherine Parry
|
09f51871c5
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lint warnings fixed
|
2021-10-12 09:45:02 -07:00 |
|
Katherine Parry
|
4ea56ac68b
|
some fpu lint warnings fixed - still working on it
|
2021-10-11 18:32:03 -07:00 |
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kipmacsaigoren
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e28d8892ad
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added historical outputs folder for synth runs
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2021-10-11 19:52:52 -05:00 |
|
Shreya Sanghai
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51185478df
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made redunantmul generate DW02_multp for synopsys sythnesis
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2021-10-11 11:54:39 -07:00 |
|
Shreya Sanghai
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295a3c7af2
|
actually added redundant mul
|
2021-10-11 11:29:13 -07:00 |
|
David Harris
|
f9b37c3ce1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-11 11:21:39 -07:00 |
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