154 Commits

Author	SHA1	Message	Date
slmnemo	a5d5bd272b	changes suggested by ben, hopefully fixing buildroot (which is now not running)	2022-05-20 18:42:38 -07:00
Katherine Parry	6bc31f2e78	Fixed unpacker bug LT EQ LE pass testfloat	2022-05-20 17:19:50 +00:00
slmnemo	6c237e43d8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-05-19 17:51:45 -07:00
slmnemo	0982417054	Fixed buildroot by adding a second .	2022-05-19 17:49:32 -07:00
slmnemo	7d2bfb6db8	parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do	2022-05-19 16:21:38 -07:00
Katherine Parry	b0881495a9	Bug fixed in unpacker and sub/add/mul tests pass TestFloat	2022-05-19 20:31:23 +00:00
Katherine Parry	cc0ab94ebc	Added fp tests - doesnpass yet	2022-05-19 16:32:30 +00:00
slmnemo	ba572b46f4	Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature.	2022-05-17 01:04:13 +00:00
slmnemo	ede0a3237d	quit	2022-05-17 01:03:09 +00:00
David Harris	730bcac6ba	Partitioned privileged pipeline registers into module	2022-05-12 20:45:45 +00:00
David Harris	21c1e58829	Partitioned privilege mode fsm into new module	2022-05-12 16:16:42 +00:00
David Harris	e2dea3bb89	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
mmasserfrye	52b0e7d567	filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv	2022-05-12 07:22:06 +00:00
David Harris	a8c9f504fa	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	91472eb948	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	66424a8246	SFENCE.VMA should be illegal in user mode	2022-05-05 15:15:02 +00:00
David Harris	c100c9893b	wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts	2022-05-05 14:37:21 +00:00
David Harris	94459ade3d	Changed WFI to stall pipeline in memory stage	2022-05-05 02:03:44 +00:00
Kip Macsai-Goren	0f70e48b6b	updated makefrag and tests.vh to reflect removed tests, new names	2022-05-04 21:20:25 +00:00
Kip Macsai-Goren	e557e420b6	added missing SIE test	2022-04-29 19:54:29 +00:00
Kip Macsai-Goren	5df381e26f	renamed PIE-stack tests to status-mie for clarity	2022-04-29 18:30:39 +00:00
Kip Macsai-Goren	c3ffcd0e95	removed old unused tests from wally arch tests	2022-04-28 18:14:08 +00:00
Kip Macsai-Goren	0e5cc40360	added 32 bit versions of new tests. all but timeout wait pass regression	2022-04-28 18:14:07 +00:00
Skylar Litz	970f6c4222	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-27 10:50:19 -07:00
Skylar Litz	594db170de	fix AttemptedInstructionCount from ground zero	2022-04-27 10:45:40 -07:00
Kip Macsai-Goren	0f4ca62157	added working tests to test list, updated regression for new configs	2022-04-25 19:18:15 +00:00
Kip Macsai-Goren	7ff85258f0	added new tests to tests.vh, comented out until they pass regression	2022-04-25 18:22:44 +00:00
David Harris	0ede295e88	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
Ross Thompson	8fcd4d47b7	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-21 09:52:42 -05:00
Kip Macsai-Goren	cd53163d9a	added new tests to tests.vh	2022-04-20 17:34:40 +00:00
Kip Macsai-Goren	510021af65	added working general trap tests to regression	2022-04-20 06:48:01 +00:00
Ross Thompson	546ef08eb2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-19 14:09:50 -05:00
Kip Macsai-Goren	64698aa806	Added working trap test to regression, fixed hanfling of some interrupts	2022-04-18 07:22:16 +00:00
Ross Thompson	a99466a487	Fixed bug I introduced by csrc cleanup and changes to ILA.	2022-04-17 21:45:46 -05:00
Ross Thompson	c409bde6ae	fixed no forcing bug in linux testbench.	2022-04-17 17:49:51 -05:00
David Harris	de5b61291f	Experiments with prefix comparator; minor fixes in WFI and testbench warnings	2022-04-17 21:43:12 +00:00
Kip Macsai-Goren	1f9c987efe	added new tests to makefrag and tests.vh	2022-04-17 21:00:36 +00:00
David Harris	a28831b83e	Added WFI to the testbench instruction name decoder	2022-04-14 17:12:11 +00:00
bbracker	fe53dd1683	fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM	2022-04-14 09:23:21 -07:00
bbracker	eb21e34000	fix ReadDataM forcing	2022-04-13 15:32:00 -07:00
Ross Thompson	2e8afd071e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-13 13:39:47 -05:00
bbracker	735c75af55	change interrupt spoofing to happen at negative clock edges	2022-04-13 04:31:23 -07:00
bbracker	52ed99ca1b	improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS	2022-04-13 03:37:53 -07:00
bbracker	03f1c01f14	whoops forgot to update AttemptedInstructionCount in interrupt spoofing	2022-04-13 00:49:37 -07:00
bbracker	d3e9703c19	change testbench-linux to by default use attempted instruction count for warning/error messages	2022-04-12 21:22:08 -07:00
Ross Thompson	fc173a7954	Missed the force on uart for no tracking.	2022-04-12 19:37:44 -05:00
Ross Thompson	f995ec2a54	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-10 13:41:27 -05:00
Ross Thompson	c3d9eafe60	Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.	2022-04-10 13:27:54 -05:00
bbracker	aa71fe542d	upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs	2022-04-08 13:45:27 -07:00
bbracker	3b6cb5f0ba	small signs of life on new interrupt spoofing	2022-04-08 12:32:30 -07:00