David Harris
38b8cc652c
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
Ross Thompson
c856003f73
RAS needs to be reset or preloaded. For now I just reset it.
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Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6
Added FlushF to hazard unit.
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Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
7d6093b302
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
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About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Ross Thompson
bbe0db3ebe
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
Ross Thompson
ca546beaf8
We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
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This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
David Harris
cc42655789
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
Ross Thompson
935e9e59e9
added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
2021-02-14 15:13:55 -06:00
Ross Thompson
8486f426b7
The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
2021-02-14 11:06:31 -06:00
David Harris
842c374de9
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
92bf1674b4
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
