David Harris
a5c0dc8c81
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
b5df9b282d
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
David Harris
ee605d7550
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
2021-07-03 03:29:33 -04:00
Ross Thompson
46831035fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-02 13:56:49 -05:00
David Harris
648c09e5ef
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
Ross Thompson
386193de00
added page table walker fault exit for icache.
2021-07-01 17:59:55 -05:00
Kip Macsai-Goren
389b9a510e
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Ross Thompson
0377d3b2c9
Progress.
2021-06-24 13:05:22 -05:00
Kip Macsai-Goren
547bf1d0af
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
6134c22aca
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
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Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Ross Thompson
d5063bee7d
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
03084a4128
Icache now uses physical lenght bits rather than XLEN.
2021-06-21 16:41:09 -05:00
David Harris
29ad38fb9e
Added Physical Address and Size to PMA Checker/MMU
2021-06-21 01:27:02 -04:00
David Harris
aef408af58
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
Ross Thompson
bb756849a7
Revert "Icache now uses physical lenght bits rather than XLEN."
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This reverts commit d4de8a54a2
2021-06-19 08:58:34 -05:00
Ross Thompson
d4de8a54a2
Icache now uses physical lenght bits rather than XLEN.
2021-06-18 12:02:59 -05:00
David Harris
a3f3533cce
Changed physical addresses to PA_BITS in size in MMU and TLB
2021-06-18 09:11:31 -04:00
David Harris
6dcf86948c
Restored PCCorrectE declaration in IFU
2021-06-09 21:09:16 -04:00
David Harris
e231fc6b00
More verilator fixes, but bpred is broken
2021-06-09 21:03:03 -04:00
David Harris
9a17556de4
Start to parameterize number of PMP Entries
2021-06-08 15:29:22 -04:00
Kip Macsai-Goren
be99c18002
making mmu branch line up with main
2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
41ceb20296
some cleanup of signals, not done yet
2021-06-08 13:39:32 -04:00
Kip Macsai-Goren
d69501c4fa
Cleaned up some unused signals
2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
4a00fbaf04
Merge branch 'mmu' into main
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new mmu unit and moving pmp/pma now passes regression except for lint and buildroot
2021-06-04 17:07:56 -04:00
Kip Macsai-Goren
7e41b17e65
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
Ross Thompson
147be536f1
Relocated the icache to the cache directoy.
2021-06-04 12:23:46 -05:00
David Harris
b836679ae1
Started MMU
2021-06-04 11:59:14 -04:00
David Harris
a61411995a
moved shared constants to a shared directory
2021-06-03 22:41:30 -04:00
Ross Thompson
db2a38c300
Fixed a few lint errors,
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clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
Ross Thompson
f5aa5d7c67
Forgot to include the new gshare predictor file.
2021-06-01 12:42:03 -05:00
Ross Thompson
8f9680556f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
Ross Thompson
1db8d0e59c
may have fixed the global branch history predictor.
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The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
bbracker
a45b61ede9
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Ross Thompson
40bdcda32d
It's a bit sloppy, but the global history predictor is working correctly now.
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There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Ross Thompson
735e511073
fixed bug with icache miss spill fsm branch.
2021-05-25 14:26:22 -05:00
Ross Thompson
13034c7406
Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
2021-05-24 23:24:54 -05:00
Ross Thompson
dd26b754eb
Fixed minor bug in instruction class decoding.
2021-05-24 13:41:14 -05:00
Ross Thompson
b06fda88ff
Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
2021-05-24 12:37:16 -05:00
Ross Thompson
2aa4db470b
Fixed synthesis bug with icache valid bit.
2021-05-04 13:03:08 -05:00
Ross Thompson
87d3869a6e
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
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I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Ross Thompson
e09ac73eaf
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
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Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
Ross Thompson
b57c187208
Fixed typo in ifu for bypassing branch predictor.
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Fixed missing signal name in local history predictor.
2021-05-03 08:56:45 -05:00
Jarred Allen
000f48cd75
Fix compile error in branch predictor
2021-04-29 14:36:56 -04:00
Shreya Sanghai
b554dc8e72
fixed bug in gshare, global and local history BP
2021-04-29 06:14:32 -04:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
a7e4d39ea1
Fixed issue with not saving the first cache block read on a miss spill.
2021-04-26 12:57:34 -05:00
