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Author	SHA1	Message	Date
David Harris	926ffc8a15	Simplified interface to fclassify and fsgn (fixed)	2021-07-22 12:33:38 -04:00
David Harris	ae29eaa98d	Simplified interface to fclassify and fsgn	2021-07-22 12:30:46 -04:00
Ross Thompson	42fe5ceee3	Cleaned up icache and dcache.	2021-07-22 11:06:44 -05:00
Ross Thompson	89e22bc5e8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-22 10:38:24 -05:00
Ross Thompson	e907d57340	Tested all numbers of ways for dcache 1, 2, 4, and 8.	2021-07-22 10:38:07 -05:00
bbracker	9dcd5d3622	fix UART RX FIFO bug where tail pointer can overtake head pointer	2021-07-22 02:09:41 -04:00
bbracker	cdcf419147	make address translator signals visible in waveview	2021-07-21 20:07:49 -04:00
bbracker	70ef670da1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-21 20:07:03 -04:00
bbracker	3c6a1f8824	replace physical address checking with virtual address checking because address translator is broken	2021-07-21 19:47:13 -04:00
bbracker	b48d179c37	hardcoded hack to fix missing STVEC vector	2021-07-21 19:34:57 -04:00
Ross Thompson	1e88784bd4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-21 16:44:32 -05:00
Kip Macsai-Goren	bb8ec549a7	fixed issue with tlbflush remaining high during a stalled sfence instruction	2021-07-21 17:43:36 -04:00
Ross Thompson	aa624625bc	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-21 16:39:07 -05:00
Ross Thompson	1f0ff804cf	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-21 14:56:30 -05:00
Ross Thompson	511c36fb1b	Improved address bus names and usages in the walker, dcache, and tlbs. ... Merge branch 'walkerEnhance' into main	2021-07-21 14:55:09 -05:00
Ross Thompson	abe57e3fd0	Added comment about better muxing.	2021-07-21 14:40:14 -05:00
Ross Thompson	3d79dc51bb	4 way set associative is now working.	2021-07-21 14:01:14 -05:00
Kip Macsai-Goren	e25b4643a8	removed remaining 32 bit loads/stores with 64 bit ones.	2021-07-21 14:45:22 -04:00
Kip Macsai-Goren	e59490d032	Fixed TLB parameterization and valid bit flop to correctly do instr page faults	2021-07-21 14:44:43 -04:00
Katherine Parry	59f79722ab	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
bbracker	e8b966c5d1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-21 13:04:11 -04:00
bbracker	f7a61a5c73	progress on recovering from QEMU's errors	2021-07-21 13:00:32 -04:00
Ross Thompson	39fc9278ba	Fixed remaining bugs in 2 way set associative dcache.	2021-07-21 10:35:23 -05:00
Ross Thompson	ba3aed8760	Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. ... Also forgot to include cacheLRU.sv file.	2021-07-20 23:17:42 -05:00
Katherine Parry	61f81bb76e	FMA parameterized	2021-07-20 22:04:21 -04:00
Kip Macsai-Goren	53945adf4a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 21:04:53 -04:00
Kip Macsai-Goren	87e3f6c36d	light cleanup	2021-07-20 20:49:07 -04:00
Kip Macsai-Goren	f6bdb7b743	added new execution tests that should work with dcache memory non-syncness with 'real memory'. They make, but don't pass regression yet	2021-07-20 20:47:20 -04:00
Kip Macsai-Goren	e9fa2e18fd	added new executable test, cheange PTE to test library	2021-07-20 20:39:00 -04:00
Ross Thompson	8d0a552b5b	Partially working 2 way set associative d cache.	2021-07-20 17:51:42 -05:00
bbracker	d6c93a50aa	fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk	2021-07-20 17:55:44 -04:00
Kip Macsai-Goren	8521aecfa6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 17:01:09 -04:00
bbracker	b5ceb6f7c3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 15:04:13 -04:00
bbracker	945c8d496f	commented out old hack that used hardcoded addresses	2021-07-20 15:03:55 -04:00
David Harris	62b3673027	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 14:46:58 -04:00
David Harris	20744883df	flag for optional boottim	2021-07-20 14:46:37 -04:00
Ross Thompson	a042c356e1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-20 13:27:58 -05:00
Ross Thompson	bb5b5e71b1	Replaced FinalReadDataM with ReadDataM in dcache.	2021-07-20 13:27:29 -05:00
Abe	38e24aacdd	Updated riscv64-unknown-elf-gcc location so that it can be easily accessed	2021-07-20 14:18:13 -04:00
bbracker	7694342d4e	ignore mhpmcounters because QEMU doesn't implement them	2021-07-20 13:37:52 -04:00
Kip Macsai-Goren	34d70426ce	Updated MMU tests to use shared library in assembly	2021-07-20 12:35:30 -04:00
bbracker	761300afcd	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 12:08:46 -04:00
David Harris	c117356432	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
bbracker	3de8461f3c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 05:40:49 -04:00
bbracker	c9775de3b2	testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)	2021-07-20 05:40:39 -04:00
James E. Stine	b36d6fe1be	slight mod to fpdiv - still bug in batch vs. non-batch	2021-07-20 01:47:46 -04:00
bbracker	5347a58192	major fixes to CSR checking	2021-07-20 00:22:07 -04:00
Ross Thompson	ae2371f2ce	Added performance counters for dcache access and dcache miss.	2021-07-19 22:12:20 -05:00
Ross Thompson	07c47f0034	Restored TIM range.	2021-07-19 21:17:31 -05:00
bbracker	a01fea69dd	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 19:30:40 -04:00