Ross Thompson
cb34b7c98f
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
Ross Thompson
cea012a640
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
89f13370e2
Removed old signals.
2022-08-31 09:50:39 -05:00
Ross Thompson
a2220fc142
Have a rough working multi manager!
2022-08-29 17:11:27 -05:00
Ross Thompson
f5584bb41c
Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu.
2022-08-29 17:04:53 -05:00
Ross Thompson
233777f744
Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.
2022-08-29 13:01:24 -05:00
David Harris
eb753b3b3f
FIxed wallypipelinedsoc merge conflict
2022-08-25 15:36:47 -07:00
David Harris
902d2067ba
Removed delayed AHB signals from top level
2022-08-25 15:34:14 -07:00
Ross Thompson
db635e3ad2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 16:01:02 -05:00
David Harris
302a7fa294
Extended HADDR to PA_BITS
2022-08-25 13:11:36 -07:00
Ross Thompson
f67010c688
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 14:40:52 -05:00
David Harris
dda3b441d7
Continued busdp/ebu simplification
2022-08-25 10:20:02 -07:00
David Harris
19fe6d106c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 09:52:49 -07:00
David Harris
aba914ea5e
Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
2022-08-25 09:52:08 -07:00
Ross Thompson
e605ef57dc
BROKEN. Don't use this commit.
...
Issue running cacheless with bus.
2022-08-25 11:02:46 -05:00
Ross Thompson
b0aea77b20
Added generate around uncore.
2022-08-25 10:35:24 -05:00
Ross Thompson
01a7718471
Added generate around ebu.
2022-08-25 09:24:13 -05:00
David Harris
5eebd521c5
Fixed FPU-IEU forwarding stall
2022-08-23 14:14:41 -07:00
David Harris
05aa18fe14
Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
2022-08-23 12:17:19 -07:00
David Harris
6cfbf95d98
Renamed signals for LSU - FPU interface
2022-08-22 13:47:56 -07:00
David Harris
ea153e0aad
Removed FStore2 and simplified HPTW
2022-08-22 13:29:54 -07:00
Ross Thompson
f3f0f12904
Removed logic from Verilog wrapper.
2022-08-21 14:07:43 -05:00
Ross Thompson
3612db2d70
pulled swbbytemask out of subword write.
2022-08-01 20:48:45 -05:00
Katherine Parry
18d7fee541
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-07-12 22:37:20 +00:00
Katherine Parry
62205ebb3b
renamed FLoad2 to FStore2
2022-07-09 00:26:45 +00:00
David Harris
5ae88dbef0
Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
2022-07-08 09:09:02 +00:00
David Harris
f865994ba1
fixing port errors
2022-07-07 21:57:10 +00:00
David Harris
72e216d053
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
Katherine Parry
8f98f3bfab
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
Katherine Parry
03d823f5d7
added fld in rv32 - needs testing
2022-06-20 22:53:13 +00:00
Katherine Parry
5f7072bd96
postprocessing unit created and passing all tests
2022-06-13 22:47:51 +00:00
slmnemo
be658d3933
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
a5aa75e5de
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
90c5e5d319
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
9065b684f8
Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit
2022-06-02 09:37:59 -07:00
David Harris
129fab3794
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
efce3e4953
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
80965f953c
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
David Harris
4c5e361b00
More unused signal cleanup
2022-05-12 15:26:08 +00:00
David Harris
5acb526375
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
fb725a9e0a
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
a8c9f504fa
Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
2022-05-11 15:08:33 +00:00
David Harris
91472eb948
Removed M suffix from interrupts because they are generated asynchronously to pipeline
2022-05-11 14:41:55 +00:00
David Harris
8066ba45e8
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
David Harris
2cdd49c7d2
WFI terminates when an interrupt is pending even if interrupts are globally disabled
2022-05-08 04:30:46 +00:00
David Harris
7024293a59
Zero'd wfiM when ZICSR not supported to fix hang in E tests
2022-05-05 15:32:13 +00:00
David Harris
94459ade3d
Changed WFI to stall pipeline in memory stage
2022-05-05 02:03:44 +00:00
David Harris
9c4de0e9c1
FPU generates illegal instruction if MSTATUS.FS = 00
2022-05-03 11:56:31 +00:00
Kip Macsai-Goren
7bc6943527
Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
2022-04-22 22:46:11 +00:00
