Ross Thompson
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9bcb105aa4
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Changed names of Icache signals.
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2021-12-30 11:01:11 -06:00 |
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Ross Thompson
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a37c7515bd
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Icache now works with any sized cache line a power of 2, greater than or equal to 32.
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2021-12-30 10:37:57 -06:00 |
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Ross Thompson
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d50a65720d
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More name cleanup in caches.
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2021-12-30 09:18:16 -06:00 |
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Ross Thompson
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d474caf24f
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Removed WAdr from cacheway as it is redundant.
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2021-12-29 21:39:43 -06:00 |
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Ross Thompson
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7765178a04
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Rename of dcache interface signals.
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2021-12-29 21:26:15 -06:00 |
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Ross Thompson
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81741925aa
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Moved LSU Bus interface control path into it's own module.
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2021-12-29 17:35:45 -06:00 |
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Ross Thompson
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050523487c
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Changed names of lsu address signals.
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2021-12-29 15:03:34 -06:00 |
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Ross Thompson
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bc437cf7e0
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Cleaned up some names in dcache and lsu.
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2021-12-29 11:21:44 -06:00 |
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Ross Thompson
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fe22d4544f
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Converted mux4 to mux3 in dcache.
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2021-12-29 10:58:02 -06:00 |
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Ross Thompson
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0c88ddeb5a
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Simplified the dcache to bus address generation.
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2021-12-29 10:46:48 -06:00 |
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Ross Thompson
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6052a69ba7
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Fixed interrupt delay bug by reverting CommittedM changes.
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2021-12-28 22:27:12 -06:00 |
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Ross Thompson
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e29803be30
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Removed CommittedM as it is redundant with LSUStall.
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2021-12-28 16:14:10 -06:00 |
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Ross Thompson
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13b4201198
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Added generate around virtual memory hardware in LSU.
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2021-12-28 15:00:02 -06:00 |
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Ross Thompson
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73af458eb5
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More cleanup of dcache.
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2021-12-28 14:12:18 -06:00 |
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Ross Thompson
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1e76c24f26
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Major cleanup of the LSU.
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2021-12-28 13:10:45 -06:00 |
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Ross Thompson
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79b17c5b55
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Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
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2021-12-28 12:33:07 -06:00 |
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Ross Thompson
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34c11ca8d5
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Minor dcache cleanup.
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2021-12-28 11:29:16 -06:00 |
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Ross Thompson
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74d636cb53
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First cut at moving the dcache bus interface into the LSU.
Regression test does not run and there is a lot of cleanup to do.
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2021-12-27 18:12:59 -06:00 |
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Ross Thompson
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d366a1f50f
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Moved dcache fetch logic outside the dcache except for the fsm.
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2021-12-27 16:45:49 -06:00 |
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Ross Thompson
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e3ddcbb11e
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Partial commit.
Moved AMO, SWW, and SWR outside the dcache.
Step 1 of separate the fetching logic from the caches.
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2021-12-27 15:56:18 -06:00 |
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Ross Thompson
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6a8e917e06
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It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
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2021-12-21 15:59:56 -06:00 |
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Ross Thompson
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7844d3f064
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Fixed bug where the wrong address is read into the icache memory.
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2021-12-21 15:16:00 -06:00 |
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Ross Thompson
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ffe792bcfc
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Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address.
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2021-12-20 23:27:37 -06:00 |
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Ross Thompson
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8feb36b926
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Signal renames.
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2021-12-19 22:21:03 -06:00 |
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Ross Thompson
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138da1fefa
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Removed lsuArb and placed remaining logic in lsu.sv.
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
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2021-12-19 21:34:40 -06:00 |
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Ross Thompson
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c453b285dc
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Fixed bug where icache did not replay PCF on itlb miss.
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2021-12-19 17:01:13 -06:00 |
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Ross Thompson
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c9291655da
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Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
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2021-12-19 16:12:31 -06:00 |
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Ross Thompson
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a445bedcd2
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Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
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2021-12-19 14:57:42 -06:00 |
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Ross Thompson
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1126135b80
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minro change. comments about needed changes in dcache.
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2021-12-19 13:53:02 -06:00 |
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Ross Thompson
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4daeb6657f
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Merge branch 'tlb_fixes' into main
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2021-12-18 12:24:17 -06:00 |
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Ross Thompson
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ee81cfff0c
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Possible fix for icache deadlock interaction with hptw.
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2021-12-17 14:38:25 -06:00 |
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David Harris
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aebd746e71
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Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
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2021-12-15 12:10:45 -08:00 |
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Ross Thompson
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6d2a4b8354
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Oups missed files in the last commit.
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2021-12-15 10:25:08 -06:00 |
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Ross Thompson
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af9f97454d
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Cleaned up fpga synthesis script.
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2021-12-13 18:26:54 -06:00 |
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Ross Thompson
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81da8b8d2a
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Formating changes to cache fsms.
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2021-12-13 17:16:13 -06:00 |
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Ross Thompson
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4d6d72a082
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Fixed some typos in the dcache ptw interaction documentation.
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2021-12-13 15:47:20 -06:00 |
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Ross Thompson
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39168a201b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-12 17:21:51 -06:00 |
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Ross Thompson
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68745d40f2
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Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
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2021-12-12 17:21:44 -06:00 |
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Ross Thompson
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37079626cd
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Fixed numerous errors in the preformance counter updates.
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
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2021-12-09 11:44:12 -06:00 |
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Ross Thompson
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5642918ead
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Merge branch 'main' into fpga
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2021-11-29 10:06:53 -06:00 |
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Ross Thompson
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705572f0ac
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Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
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2021-11-20 22:35:47 -06:00 |
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Ross Thompson
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9c875d38a9
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Fixed the 4 way set associative pseudo LRU replacement policy.
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2021-10-29 12:46:02 -05:00 |
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Ross Thompson
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41dbb59e24
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Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
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2021-10-29 11:03:37 -05:00 |
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Ross Thompson
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35fcadbe7f
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Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
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2021-10-28 11:07:18 -05:00 |
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Ross Thompson
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c4170ece27
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Replaced async reset flip flops with sync reset flip flops in cache and bpread.
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2021-10-27 09:57:11 -05:00 |
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David Harris
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426a43f77b
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Forgot to save cacheway merge
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2021-10-26 08:38:13 -07:00 |
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David Harris
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c0145c0a35
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merging changes
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2021-10-26 08:34:36 -07:00 |
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David Harris
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8287a1ef3e
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Synchronous reset in non-flop blocks
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2021-10-26 08:30:35 -07:00 |
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Ross Thompson
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c43b19120f
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Fixed another critical path in the caches.
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2021-10-25 22:05:11 -05:00 |
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Ross Thompson
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1228dbbebc
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Fixed the timing issue in the cache replacement polcy.
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2021-10-25 18:00:23 -05:00 |
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