Ross Thompson d366a1f50f Moved dcache fetch logic outside the dcache except for the fsm.		2021-12-27 16:45:49 -06:00
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cachereplacementpolicy.sv	Fixed the 4 way set associative pseudo LRU replacement policy.	2021-10-29 12:46:02 -05:00
cacheway.sv	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
dcache_ptw_interaction_README.txt	Fixed some typos in the dcache ptw interaction documentation.	2021-12-13 15:47:20 -06:00
dcache.sv	Moved dcache fetch logic outside the dcache except for the fsm.	2021-12-27 16:45:49 -06:00
dcachefsm.sv	It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.	2021-12-21 15:59:56 -06:00
icache.sv	Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.	2021-12-19 14:57:42 -06:00
icachefsm.sv	Fixed bug where the wrong address is read into the icache memory.	2021-12-21 15:16:00 -06:00
sram1rw.sv	Fixed bug with the changes to sram1rw.	2021-10-25 16:11:41 -05:00