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Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.

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This commit is contained in:
Ross Thompson 2021-12-28 12:11:45 -06:00
parent 34c11ca8d5
commit 79b17c5b55
7 changed files with 22 additions and 85 deletions
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2
wally-pipelined/src/cache/icache.sv vendored
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@ -48,7 +48,6 @@ module icache
output logic ICacheStallF,
input logic ITLBMissF,
input logic ITLBWriteF,
input logic WalkerInstrPageFaultF,
input logic InvalidateICacheM,
// The raw (not decompressed) instruction that was requested
@ -289,7 +288,6 @@ module icache
.ICacheStallF,
.ITLBMissF,
.ITLBWriteF,
.WalkerInstrPageFaultF,
.ExceptionM,
.PendingInterruptM,
.InstrAckF,

29
wally-pipelined/src/cache/icachefsm.sv vendored
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@ -34,7 +34,6 @@ module icachefsm
// inputs from mmu
input logic ITLBMissF,
input logic ITLBWriteF,
input logic WalkerInstrPageFaultF,
input logic ExceptionM, PendingInterruptM,
@ -334,31 +333,8 @@ module icachefsm
NextState = STATE_READY;
end
end
/* -----\/----- EXCLUDED -----\/-----
STATE_TLB_MISS: begin
if (WalkerInstrPageFaultF) begin
NextState = STATE_READY;
ICacheStallF = 1'b0;
end else if (ITLBWriteF) begin
NextState = STATE_TLB_MISS_DONE;
ICacheStallF = 1'b1;
end else begin
NextState = STATE_TLB_MISS;
ICacheStallF = 1'b0;
end
end
STATE_TLB_MISS_DONE: begin
SelAdr = 2'b01;
NextState = STATE_READY;
end
-----/\----- EXCLUDED -----/\----- */
STATE_CPU_BUSY: begin
ICacheStallF = 1'b0;
/* -----\/----- EXCLUDED -----\/-----
if (ITLBMissF) begin
NextState = STATE_TLB_MISS;
end else
-----/\----- EXCLUDED -----/\----- */
if(StallF) begin
NextState = STATE_CPU_BUSY;
SelAdr = 2'b01;
@ -370,11 +346,6 @@ module icachefsm
STATE_CPU_BUSY_SPILL: begin
ICacheStallF = 1'b0;
ICacheReadEn = 1'b1;
/* -----\/----- EXCLUDED -----\/-----
if (ITLBMissF) begin
NextState = STATE_TLB_MISS;
end else
-----/\----- EXCLUDED -----/\----- */
if(StallF) begin
NextState = STATE_CPU_BUSY_SPILL;
SelAdr = 2'b10;

2
wally-pipelined/src/ifu/ifu.sv
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@ -74,7 +74,6 @@ module ifu (
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP,
input logic ITLBWriteF, ITLBFlushF,
input logic WalkerInstrPageFaultF,
output logic ITLBMissF,
@ -172,7 +171,6 @@ module ifu (
.PCNextF(PCNextFPhys),
.PCPF(PCPFmmu),
.PCF,
.WalkerInstrPageFaultF,
.InvalidateICacheM);
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);

43
wally-pipelined/src/lsu/lsu.sv
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@ -83,9 +83,6 @@ module lsu
output logic [`XLEN-1:0] PTE,
output logic [1:0] PageType,
output logic ITLBWriteF,
output logic WalkerInstrPageFaultF,
output logic WalkerLoadPageFaultM,
output logic WalkerStorePageFaultM,
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
@ -120,7 +117,6 @@ module lsu
logic CommittedMfromDCache;
logic CommittedMfromBus;
logic PendingInterruptMtoDCache;
logic WalkerPageFaultM;
logic AnyCPUReqM;
logic MemAfterIWalkDone;
@ -129,7 +125,6 @@ module lsu
typedef enum {STATE_T0_READY,
STATE_T0_REPLAY,
STATE_T0_FAULT_REPLAY,
STATE_T3_DTLB_MISS,
STATE_T4_ITLB_MISS,
STATE_T5_ITLB_MISS,
@ -138,8 +133,9 @@ module lsu
statetype InterlockCurrState, InterlockNextState;
logic InterlockStall;
logic SelReplayCPURequest;
logic WalkerInstrPageFaultRaw;
logic IgnoreRequest;
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
@ -156,18 +152,13 @@ module lsu
else InterlockNextState = STATE_T0_READY;
STATE_T0_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_REPLAY;
else InterlockNextState = STATE_T0_READY;
STATE_T3_DTLB_MISS: if(WalkerLoadPageFaultM | WalkerStorePageFaultM) InterlockNextState = STATE_T0_READY;
else if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY;
STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY;
else InterlockNextState = STATE_T3_DTLB_MISS;
STATE_T4_ITLB_MISS: if(WalkerInstrPageFaultRaw | ITLBWriteF) InterlockNextState = STATE_T0_READY;
STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY;
else InterlockNextState = STATE_T4_ITLB_MISS;
STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY;
else if(WalkerInstrPageFaultRaw) InterlockNextState = STATE_T0_FAULT_REPLAY;
else InterlockNextState = STATE_T5_ITLB_MISS;
STATE_T0_FAULT_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_FAULT_REPLAY;
else InterlockNextState = STATE_T0_READY;
STATE_T7_DITLB_MISS: if(WalkerStorePageFaultM | WalkerLoadPageFaultM) InterlockNextState = STATE_T0_READY;
else if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS;
STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS;
else InterlockNextState = STATE_T7_DITLB_MISS;
default: InterlockNextState = STATE_T0_READY;
endcase
@ -178,8 +169,8 @@ module lsu
// this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates
// everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0.
assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) |
(InterlockCurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (InterlockCurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) |
(InterlockCurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (InterlockCurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
(InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
-----/\----- EXCLUDED -----/\----- */
@ -187,25 +178,23 @@ module lsu
InterlockStall = 1'b0;
case(InterlockCurrState)
STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
STATE_T3_DTLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
STATE_T4_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
STATE_T3_DTLB_MISS: InterlockStall = 1'b1;
STATE_T4_ITLB_MISS: InterlockStall = 1'b1;
STATE_T5_ITLB_MISS: InterlockStall = 1'b1;
//STATE_T0_FAULT_REPLAY: if (~WalkerInstrPageFaultF) InterlockStall = 1'b1;
STATE_T7_DITLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
STATE_T7_DITLB_MISS: InterlockStall = 1'b1;
default: InterlockStall = 1'b0;
endcase
end
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY) | (InterlockNextState == STATE_T0_FAULT_REPLAY);
assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY);
assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) |
((InterlockCurrState == STATE_T0_REPLAY | InterlockCurrState == STATE_T0_FAULT_REPLAY)
((InterlockCurrState == STATE_T0_REPLAY)
& (ExceptionM | PendingInterruptM));
assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | InterlockCurrState == STATE_T0_FAULT_REPLAY;
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
@ -217,13 +206,13 @@ module lsu
.DTLBMissM(DTLBMissM & ~PendingInterruptM),
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
.HPTWReadPTE(ReadDataM),
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM,
.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
.WalkerLoadPageFaultM, .WalkerStorePageFaultM);
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM);
assign LSUStall = DCacheStall | InterlockStall | BusStall;
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
// arbiter between IEU and hptw

18
wally-pipelined/src/mmu/hptw.sv
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@ -45,15 +45,14 @@ module hptw
(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
output logic [`PA_BITS-1:0] HPTWAdr,
output logic HPTWRead, // HPTW requesting to read memory
output logic [2:0] HPTWSize, // 32 or 64 bit access.
output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
output logic [2:0] HPTWSize // 32 or 64 bit access.
);
typedef enum {L0_ADR, L0_RD,
L1_ADR, L1_RD,
L2_ADR, L2_RD,
L3_ADR, L3_RD,
LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
LEAF, IDLE} statetype; // *** placed outside generate statement to remove synthesis errors
generate
if (`MEM_VIRTMEM) begin
@ -102,11 +101,6 @@ module hptw
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
// Raise faults. DTLBMiss
assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBWalk;
assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBWalk & ~MemWrite;
assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBWalk & MemWrite;
// FSM to track PageType based on the levels of the page table traversed
flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
always_comb
@ -176,7 +170,6 @@ module hptw
L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
//else NextWalkerState = FAULT;
else NextWalkerState = LEAF;
L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
else NextWalkerState = L1_ADR;
@ -186,7 +179,6 @@ module hptw
L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
//else NextWalkerState = FAULT;
else NextWalkerState = LEAF;
L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
else NextWalkerState = L0_ADR;
@ -195,17 +187,12 @@ module hptw
// else NextWalkerState = FAULT;
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
//else NextWalkerState = FAULT;
else NextWalkerState = LEAF;
L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
else NextWalkerState = LEAF;
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
// else NextWalkerState = FAULT;
LEAF: NextWalkerState = IDLE; // updates TLB
/* -----\/----- EXCLUDED -----\/-----
FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT; /// **** BUG: Stays in fault 1 cycle longer than it should.
else NextWalkerState = IDLE;
-----/\----- EXCLUDED -----/\----- */
default: begin
// synthesis translate_off
$error("Default state in HPTW should be unreachable");
@ -215,7 +202,6 @@ module hptw
endcase
end else begin // No Virtual memory supported; tie HPTW outputs to 0
assign HPTWRead = 0;
assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
assign HPTWAdr = 0;
assign HPTWSize = 3'b000;
end

7
wally-pipelined/src/privileged/privileged.sv
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@ -50,7 +50,6 @@ module privileged (
input logic DCacheAccess,
input logic PrivilegedM,
input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
input logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM,
input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
input logic LoadMisalignedFaultM,
input logic StoreMisalignedFaultM,
@ -202,9 +201,9 @@ module privileged (
// lookup or a improperly formatted page table during walking
// *** merge these at the lsu level.
assign InstrPageFaultF = ITLBInstrPageFaultF || WalkerInstrPageFaultF;
assign LoadPageFaultM = DTLBLoadPageFaultM || WalkerLoadPageFaultM;
assign StorePageFaultM = DTLBStorePageFaultM || WalkerStorePageFaultM;
assign InstrPageFaultF = ITLBInstrPageFaultF;
assign LoadPageFaultM = DTLBLoadPageFaultM;
assign StorePageFaultM = DTLBStorePageFaultM;
// pipeline fault signals
flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,

6
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -75,7 +75,6 @@ module wallypipelinedhart (
logic InstrMisalignedFaultM;
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM;
logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM;
logic LoadMisalignedFaultM, LoadAccessFaultM;
logic StoreMisalignedFaultM, StoreAccessFaultM;
logic [`XLEN-1:0] InstrMisalignedAdrM;
@ -189,7 +188,7 @@ module wallypipelinedhart (
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
.STATUS_MPP, .ITLBWriteF, .ITLBFlushF,
.WalkerInstrPageFaultF, .ITLBMissF,
.ITLBMissF,
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
@ -270,8 +269,6 @@ module wallypipelinedhart (
.StoreAccessFaultM, // connects to privilege
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF,
.WalkerInstrPageFaultF, .WalkerLoadPageFaultM,
.WalkerStorePageFaultM,
.LSUStall); // change to LSUStall
@ -323,7 +320,6 @@ module wallypipelinedhart (
.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
.WalkerInstrPageFaultF, .WalkerLoadPageFaultM, .WalkerStorePageFaultM,
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
.LoadMisalignedFaultM, .StoreMisalignedFaultM,
.TimerIntM, .ExtIntM, .SwIntM,