Ross Thompson 705572f0ac Fixed a very complex interaction between interrupts, the icache, dcache, and hptw. ... If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table walk should be aborted before starting.		2021-11-20 22:35:47 -06:00
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cachereplacementpolicy.sv	Fixed the 4 way set associative pseudo LRU replacement policy.	2021-10-29 12:46:02 -05:00
cacheway.sv	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
dcache_ptw_interaction_README.txt	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
dcache.sv	Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.	2021-10-28 11:07:18 -05:00
dcachefsm.sv	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
icache.sv	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
icachefsm.sv	Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.	2021-11-20 22:35:47 -06:00
sram1rw.sv	Fixed bug with the changes to sram1rw.	2021-10-25 16:11:41 -05:00