Ross Thompson
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9adcf86a40
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Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
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2021-12-19 14:57:42 -06:00 |
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Ross Thompson
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0257c08641
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Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
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2021-12-19 14:00:30 -06:00 |
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Ross Thompson
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620f4a58d4
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Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states.
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2021-12-19 13:55:57 -06:00 |
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Ross Thompson
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fdf493bd47
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minro change. comments about needed changes in dcache.
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2021-12-19 13:53:02 -06:00 |
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Ross Thompson
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f601b3ae53
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Merge branch 'tlb_fixes' into main
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2021-12-18 12:24:17 -06:00 |
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David Harris
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852c521328
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Shared ALU mux input for shifts
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2021-12-18 10:08:52 -08:00 |
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David Harris
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a7d7f852a6
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Factored out common parts of shifter
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2021-12-18 10:01:12 -08:00 |
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David Harris
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7868c0da55
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Cleaning shifter
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2021-12-18 09:43:09 -08:00 |
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David Harris
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b453454b24
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Moved W64 truncation after result mux
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2021-12-18 09:27:25 -08:00 |
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David Harris
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2a5a7eff82
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Forwarding logic factoring
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2021-12-18 05:40:38 -08:00 |
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David Harris
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1212e21eba
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Simplified FWriteInt interfaces by merging into RegWrite
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2021-12-18 05:36:32 -08:00 |
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Ross Thompson
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5264577dcf
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Possible fix for icache deadlock interaction with hptw.
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2021-12-17 14:38:25 -06:00 |
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David Harris
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3a9071e509
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Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
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2021-12-15 12:10:45 -08:00 |
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David Harris
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f0059b7b3a
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IEU cleanup:
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2021-12-15 11:38:26 -08:00 |
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Ross Thompson
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9f798250ea
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Oups missed files in the last commit.
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2021-12-15 10:25:08 -06:00 |
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David Harris
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f4957fdac1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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Ross Thompson
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45b38ea9fe
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Comments for dcache and icache refactoring.
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2021-12-14 14:46:29 -06:00 |
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David Harris
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eb33021f40
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-14 11:15:58 -08:00 |
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David Harris
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dd0d4c0add
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ALU and datapath cleanup
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2021-12-14 11:15:47 -08:00 |
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Ross Thompson
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f061a26411
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Cleaned up fpga synthesis script.
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2021-12-13 18:26:54 -06:00 |
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Ross Thompson
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b9c8b808ea
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-13 17:16:20 -06:00 |
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Ross Thompson
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7d00649b61
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Formating changes to cache fsms.
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2021-12-13 17:16:13 -06:00 |
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Ross Thompson
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5361f69639
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Fixed some typos in the dcache ptw interaction documentation.
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2021-12-13 15:47:20 -06:00 |
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David Harris
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74cf0eb96a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-13 07:57:49 -08:00 |
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David Harris
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1ca949c0bb
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Simplified ALU and source multiplexers pass tests
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2021-12-13 07:57:38 -08:00 |
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kwan
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5ede8126fd
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priviledge .* removed, passed regression
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2021-12-13 00:34:43 -08:00 |
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kwan
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b05bc3c19e
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test
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2021-12-13 00:31:51 -08:00 |
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kwan
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83dae9d774
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priviledge .* fixed, passed local regression
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2021-12-13 00:22:01 -08:00 |
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Ross Thompson
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8e39034dbd
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-12 17:33:29 -06:00 |
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Ross Thompson
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2f282e5570
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Revert "Privilige .*s removed"
This reverts commit 471f267987.
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2021-12-12 17:31:57 -06:00 |
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Ross Thompson
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fdbb7b6ef3
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Revert "Priviledged .* removed"
This reverts commit 96ac298596.
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2021-12-12 17:31:39 -06:00 |
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Ross Thompson
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547093b705
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-12 17:21:51 -06:00 |
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Ross Thompson
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bb79f70a63
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Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
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2021-12-12 17:21:44 -06:00 |
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Ross Thompson
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b88ec949cf
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Added proper credit to Richard Davis, the author of the original sd card reader.
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2021-12-12 15:05:50 -06:00 |
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kwan
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96ac298596
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Priviledged .* removed
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2021-12-12 09:55:45 -08:00 |
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kwan
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471f267987
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Privilige .*s removed
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2021-12-12 09:54:14 -08:00 |
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David Harris
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d3c3ab3e85
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-12 05:49:31 -08:00 |
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Ross Thompson
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cd59809e42
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Fixed numerous errors in the preformance counter updates.
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
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2021-12-09 11:44:12 -06:00 |
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slmnemo
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3ff994f50d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
help
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2021-12-08 14:09:58 -08:00 |
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slmnemo
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094f45e28b
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Removed .* from /wally-pipelined/src/uncore/uart.sv
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2021-12-08 14:02:53 -08:00 |
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Ross Thompson
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a55018b67a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-08 15:50:43 -06:00 |
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Ross Thompson
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3bdda9687a
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Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.
Remove preload from dtim.
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2021-12-08 15:50:15 -06:00 |
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David Harris
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9e2c3bef3c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 13:48:49 -08:00 |
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David Harris
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0b63c1cede
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Refactored IEU/ALU logic
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2021-12-08 13:48:04 -08:00 |
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Noah Limpert
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e97dd080a0
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updated fcmp.sv instantiation to remove x*'s
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2021-12-08 13:34:33 -08:00 |
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David Harris
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a174c8b4d7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 12:33:59 -08:00 |
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David Harris
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5d4014d351
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Refactoring ALU and datapath muxes
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2021-12-08 12:33:53 -08:00 |
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slmnemo
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d58f318d39
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Removed .*s from wally-pipelined/src/uncore/uncore.sv
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2021-12-08 01:03:02 -08:00 |
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slmnemo
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52b4802600
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 00:26:13 -08:00 |
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Noah Limpert
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feb21d1c4a
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removed .* instantiation from ieu.sv and datapth.sv in ieu folder
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2021-12-08 00:24:27 -08:00 |
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