Ross Thompson
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98d4929c57
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Reduced complexity of logic supressing cache operations.
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2022-11-01 15:23:24 -05:00 |
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Ross Thompson
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f9a04c13df
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comment updates.
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2022-10-22 16:28:44 -05:00 |
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Ross Thompson
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e5cae3bfa0
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Moving interlockfsm changes to a temporary branch.
reduced complexity of cache mux controls.
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2022-10-19 15:08:23 -05:00 |
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Ross Thompson
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92d7be645b
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Reordered the eviction and fetch in cache so it follows a more logical order.
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2022-10-04 17:36:07 -05:00 |
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Ross Thompson
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52e8e0f5ef
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Modified cache lru to not have the delayed write.
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2022-10-04 15:14:58 -05:00 |
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Ross Thompson
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afc6934249
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Possible fix to the bus cache interaction.
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2022-09-27 11:34:33 -05:00 |
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Ross Thompson
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dfe6bdd06d
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Found a hidden bug in the cache to bus fsm interlock.
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2022-09-26 17:41:30 -05:00 |
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Ross Thompson
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fd2a8e621a
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Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
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2022-09-26 12:48:26 -05:00 |
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Ross Thompson
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dcc00ef4b3
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Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
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2022-09-23 11:46:53 -05:00 |
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Ross Thompson
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8a6ca027c2
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The valid and dirty bits match the SRAM implementation now.
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2022-09-22 16:09:09 -05:00 |
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Ross Thompson
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29087812e1
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Solved the sram write first / read first issue. Works correctly with read first now.
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2022-09-22 14:16:26 -05:00 |
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Ross Thompson
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cdc80c1f28
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Moved other SRAMs to generic/mem.
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2022-09-21 12:36:03 -05:00 |
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Ross Thompson
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91fcca9d17
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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d6fa8d51d7
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Modified sram1p1rw to support 3 different implementation styles.
SRAM, Read first, and Write first.
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2022-09-21 11:26:00 -05:00 |
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Ross Thompson
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2ae62c2869
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pipelining of fetch into evict AHB requests.
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2022-09-13 17:51:55 -05:00 |
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Ross Thompson
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8618045bf2
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Optimization. Able to remove hptw address muxes from the E stage.
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2022-09-08 15:51:18 -05:00 |
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Ross Thompson
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d6d1c5d66d
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Moved files around.
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2022-08-31 14:08:06 -05:00 |
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Ross Thompson
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68e54977fe
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More cleanup.
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2022-08-31 11:12:38 -05:00 |
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Ross Thompson
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0b41ed63f1
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More simplifications.
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2022-08-31 10:45:16 -05:00 |
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Ross Thompson
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ddd9c507fe
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Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier.
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2022-08-31 10:36:30 -05:00 |
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Ross Thompson
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6122c03e39
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Removed unused old versions of the bus controllers.
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2022-08-31 09:51:54 -05:00 |
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Ross Thompson
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1c248e5164
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Removed old signals.
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2022-08-31 09:50:39 -05:00 |
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Ross Thompson
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5b8f888e21
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Maybe fixed it?
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2022-08-30 18:08:34 -05:00 |
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Ross Thompson
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96793d15c0
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more progress.
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2022-08-30 17:32:32 -05:00 |
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Ross Thompson
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63a824cca1
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More progress.
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2022-08-30 15:27:19 -05:00 |
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Ross Thompson
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a532eb61ba
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Progress.
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2022-08-30 14:17:00 -05:00 |
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Ross Thompson
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c8a5d61cbb
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new cache bus fsm not working but lints.
Forgot a few files in the last commit.
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2022-08-30 10:58:07 -05:00 |
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David Harris
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af2e71046e
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Fixed rv32e LSU and IFU issues
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2022-08-25 20:02:38 -07:00 |
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David Harris
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d7be94fab2
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Cleaned up SelBusWord
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2022-08-25 11:18:13 -07:00 |
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David Harris
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cd02c894df
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renamed BusBuffer to FetchBuffer
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2022-08-25 10:44:39 -07:00 |
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Ross Thompson
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bc0edc7bdf
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Updated ila signals.
Improve fpga wave config.
added back in the fpga preload.
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2022-08-25 09:03:29 -05:00 |
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Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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92c3cdc27d
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Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
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2022-08-21 15:28:29 -05:00 |
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Ross Thompson
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96d6218078
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Possible reduction of ignorerequest.
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2022-08-19 18:07:44 -05:00 |
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Ross Thompson
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5301444a61
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Changed signal names.
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2022-08-17 16:12:04 -05:00 |
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Ross Thompson
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970a90dd72
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Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
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2022-08-17 16:09:20 -05:00 |
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Ross Thompson
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acd920ae2f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-01 22:09:11 -05:00 |
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Ross Thompson
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f7e64fcd69
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Fixed fstore2 in cache?
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2022-08-01 22:04:44 -05:00 |
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Ross Thompson
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171cf7413b
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Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
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2022-08-01 21:08:14 -05:00 |
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Katherine Parry
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de03954946
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re-added FStore2 in Cache
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2022-07-29 22:54:49 +00:00 |
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Ross Thompson
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f1bd2524b7
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Don't use this commit yet. Untested.
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2022-07-24 15:40:52 -05:00 |
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Ross Thompson
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334008630f
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Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
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2022-07-24 01:20:29 -05:00 |
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Ross Thompson
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856ac24686
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Removed replay from the config files.
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2022-07-24 00:34:11 -05:00 |
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Ross Thompson
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458bfbf6f6
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Merged evict dirty clear with flush write back.
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2022-07-24 00:22:43 -05:00 |
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Ross Thompson
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5cd6c8069d
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signal name cleanup.
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2022-07-22 23:36:27 -05:00 |
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Ross Thompson
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7d026e02f2
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cache cleanup after removing replay on cpubusy.
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2022-07-22 23:30:25 -05:00 |
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Ross Thompson
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706bc819e1
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cache fsm cleanup after removal of replay.
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2022-07-22 23:25:09 -05:00 |
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Ross Thompson
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0f586c9ed3
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Possible improvement to cache which removes the cpu_busy states.
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2022-07-22 23:20:37 -05:00 |
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Ross Thompson
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9868e685a4
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Minor cleanup of cache.
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2022-07-19 23:04:23 -05:00 |
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Ross Thompson
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6c8ac7851e
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Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
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2022-07-19 22:42:25 -05:00 |
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